公开(公告)号：US10204920B2

公开(公告)日：2019-02-12

申请号：US15095579

申请日：2016-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JinTae Kim ,  Jaewan Choi

IPC: H01L27/118 ,  G06F17/50 ,  H01L27/02

Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.

公开(公告)号：US10332798B2

公开(公告)日：2019-06-25

申请号：US15624039

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  JinTae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC: H01L21/8238 ,  H01L27/06 ,  G06F17/50 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/02

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：USRE49545E1

公开(公告)日：2023-06-06

申请号：US17175381

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JinTae Kim ,  Jaewan Choi

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11859 ,  H01L2027/11874 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.