公开(公告)号：US11043428B2

公开(公告)日：2021-06-22

申请号：US16450383

申请日：2019-06-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ha-Young Kim ,  Jin Tae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC分类号： H01L27/02 ,  H01L21/8234 ,  G06F30/392 ,  H01L21/768 ,  G06F30/398 ,  H01L21/8238 ,  H01L27/06

摘要： A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US10332798B2

公开(公告)日：2019-06-25

申请号：US15624039

申请日：2017-06-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ha-Young Kim ,  JinTae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC分类号： H01L21/8238 ,  H01L27/06 ,  G06F17/50 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/02

摘要： A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US09698056B2

公开(公告)日：2017-07-04

申请号：US15094764

申请日：2016-04-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ha-Young Kim ,  Jin Tae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC分类号： H01L27/06 ,  H01L21/768 ,  G06F17/50 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/8238

CPC分类号： H01L21/823475 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629

摘要： A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.