公开(公告)号：US20250063782A1

公开(公告)日：2025-02-20

申请号：US18592999

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Jintae Kim ,  Kang-ill Seo

IPC: H01L29/417 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a wimpy transistor stack on a substrate, wherein the wimpy transistor stack comprises: an upper transistor comprising: a plurality of upper channel regions stacked in a vertical direction; and an upper source/drain region that contacts at least one of the plurality of upper channel regions; a lower transistor that is between the substrate and the upper transistor and comprises: a plurality of lower channel regions stacked in the vertical direction; and a lower source/drain region that contacts at least one of the plurality of lower channel regions; and a source/drain isolation layer separating the upper source/drain region from the lower source/drain region, wherein the source/drain isolation layer contacts a lowermost one of the plurality of upper channel regions and/or an uppermost one of the plurality of lower channel regions.

公开(公告)号：US12051696B2

公开(公告)日：2024-07-30

申请号：US17840060

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Panjae Park ,  Jaeseok Yang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5286 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

公开(公告)号：US20250105153A1

公开(公告)日：2025-03-27

申请号：US18752851

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L23/48 ,  H01L27/092

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.

公开(公告)号：US20250063811A1

公开(公告)日：2025-02-20

申请号：US18593051

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Jintae Kim ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit device includes a wimpy transistor stack and a reference transistor stack on a substrate. The wimpy transistor stack may include a first intergate insulator that is thicker than a second intergate insulator of the reference transistor stack. Due to the thicker first intergate insulator, a number of first upper channel regions of the wimpy transistor stack may be less than a number of second upper channel regions of reference transistor stack, and/or a number of first lower channel regions of the wimpy transistor stack may be less than a number of second lower channel regions of the reference transistor stack.

公开(公告)号：US20250159980A1

公开(公告)日：2025-05-15

申请号：US18758376

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Panjae Park ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having lower channel layers and a lower gate material that is between the lower channel layers. The stacked FET device includes an upper FET that is on the lower FET. The upper FET has upper channel layers and an upper gate material that is between the upper channel layers. Moreover, the stacked FET device includes an insulating layer that is between the lower gate material and the upper gate material and not in a region in which the lower channel layers are overlapped by the upper channel layers. Related methods of forming stacked FET devices are also provided.

公开(公告)号：US20240282855A1

公开(公告)日：2024-08-22

申请号：US18228231

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myunghoon JUNG ,  Panjae Park ,  Jaejik Baek ,  Seungchan Yun ,  Myung Yang ,  Kang-ill Seo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66666

Abstract: Provided is a semiconductor device including a 3DSFET device which includes: a 1st source/drain region; a 2nd source/drain region, above the 1st source/drain region, having a smaller width than the 1st source/drain region, the 2nd source/drain region being isolated from the 1st source/drain region by a 1st isolation structure; a 1st contact plug on the 1st source/drain region; a 2nd contact plug on the 2nd source/drain region; and a 2nd isolation structure, between the 1st contact plug and the 2nd contact plug, isolating the 2nd contact plug from the 1st contact plug, wherein the 2nd isolation structure is different and separate from the 1st isolation structure.

公开(公告)号：US20250118676A1

公开(公告)日：2025-04-10

申请号：US18433145

申请日：2024-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Panjae Park ,  Hyojong Shin ,  Kang-ill Seo

IPC: H01L23/538 ,  H01L27/02

Abstract: Provided is a semiconductor device which may include: a plurality of gate structures arranged at a predetermined gate pitch in a 1st direction and extended in a 2nd direction; and a plurality of metal lines arranged at two or more different metal pitches in the 1st direction and extended in the 2nd direction at a same level in a 3rd direction.

公开(公告)号：US20240355878A1

公开(公告)日：2024-10-24

申请号：US18456571

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG MIN SONG ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L25/07 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L25/074 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode. The lower gate electrode may be electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact may protrude beyond a side surface of the lower gate electrode.

公开(公告)号：US11387234B2

公开(公告)日：2022-07-12

申请号：US16910385

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Panjae Park ,  Jaeseok Yang

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

公开(公告)号：US20240421154A1

公开(公告)日：2024-12-19

申请号：US18488412

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Wonhyuk Hong ,  Tae Sun Kim ,  Panjae Park ,  Kang-ill Seo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.