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    MEMORY CHIP
    1.
    发明公开
    MEMORY CHIP 审中-公开

    公开(公告)号：US20240312555A1

    公开(公告)日：2024-09-19

    申请号：US18303580

    申请日：2023-04-20

    申请人： Winbond Electronics Corp.

    发明人： Ying-Te Tu

    IPC分类号： G11C29/54 ,  G11C5/02 ,  G11C5/14

    CPC分类号： G11C29/54 ,  G11C5/025 ,  G11C5/144

    摘要： Disclosed is a memory chip including a plurality of first power pads and a first bus. The first bus is connected to the first power pads. One of the first power pads is coupled to the first bus via a switch device. A data width of the memory chip is determined according to a conduction state of the switch device.

    Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration
    2.
    发明授权
    Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration 有权

    公开(公告)号：US12087350B2

    公开(公告)日：2024-09-10

    申请号：US17032191

    申请日：2020-09-25

    申请人： Intel Corporation

    发明人： William Waller ,  Cheng-Yi Huang

    IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4094

    CPC分类号： G11C11/4087 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4085 ,  G11C11/4094

    摘要： Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.

    SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME
    8.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开

    公开(公告)号：US20240221799A1

    公开(公告)日：2024-07-04

    申请号：US18609522

    申请日：2024-03-19

    申请人： KIOXIA CORPORATION

    发明人： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

    IPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/22

    CPC分类号： G11C7/1063 ,  G11C5/025 ,  G11C7/222

    摘要： In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

    Sub-Word Line Driver Placement For Memory Device
    10.
    发明公开
    Sub-Word Line Driver Placement For Memory Device 审中-公开

    公开(公告)号：US20240185911A1

    公开(公告)日：2024-06-06

    申请号：US18443979

    申请日：2024-02-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

    IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

    CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

    摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.