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公开(公告)号:US12040889B2
公开(公告)日:2024-07-16
申请号:US18076104
申请日:2022-12-06
申请人: Intel Corporation
发明人: Matthew Adiletta , Aaron Gorius , Myles Wilde , Michael Crocker
IPC分类号: H04L41/14 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G06F15/16 , G06F16/901 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04B10/25 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14 , B25J15/00 , B65G1/04 , G05D23/19 , G05D23/20 , G06F9/38 , G06F9/50 , G06F11/14 , G06F11/34 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F13/42 , G06F15/80 , G06Q10/06 , G06Q10/0631 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/00 , G11C5/06 , H04J14/00 , H04L9/06 , H04L9/14 , H04L9/32 , H04L12/28 , H04L41/02 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/70 , H04L47/765 , H04L47/78 , H04L47/80 , H04L49/15 , H04L49/55 , H04L61/00 , H04L67/00 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/51 , H04Q1/04 , H04W4/02 , H04W4/80 , H05K1/02 , H05K1/18 , H05K5/02 , H05K7/20 , H05K13/04
CPC分类号: H04L43/08 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G06F1/183 , G06F1/20 , G06F3/0613 , G06F3/0625 , G06F3/064 , G06F3/0653 , G06F3/0655 , G06F3/0664 , G06F3/0665 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/4401 , G06F9/544 , G06F12/109 , G06F12/1408 , G06F13/1668 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F15/161 , G06F16/9014 , G08C17/02 , G11C5/02 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/3086 , H03M7/4056 , H03M7/4081 , H04B10/25891 , H04L41/145 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/357 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/0003 , H05K7/1442 , B25J15/0014 , B65G1/0492 , G05D23/1921 , G05D23/2039 , G06F3/061 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0631 , G06F3/0638 , G06F3/0647 , G06F3/0658 , G06F3/0659 , G06F3/067 , G06F9/3887 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F13/161 , G06F13/1694 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C2200/00 , G11C5/06 , H03M7/30 , H03M7/3084 , H03M7/40 , H03M7/4031 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04J14/00 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/15 , H04L49/555 , H04L61/00 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/34 , H04L67/51 , H04Q1/04 , H04Q11/00 , H04Q11/0005 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/00 , Y02P90/30 , Y04S10/50 , Y04S10/52 , Y10S901/01
摘要: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.
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公开(公告)号:US11886339B2
公开(公告)日:2024-01-30
申请号:US17750989
申请日:2022-05-23
IPC分类号: G06F12/08 , G06F12/0802 , G06F12/1009 , G06F12/02 , H04L9/32 , H04L9/08
CPC分类号: G06F12/0802 , G06F12/0246 , G06F12/1009 , H04L9/0861 , H04L9/3247 , G06F2212/402 , G06F2212/7201
摘要: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.
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公开(公告)号:US11822663B2
公开(公告)日:2023-11-21
申请号:US17107569
申请日:2020-11-30
申请人: Red Hat, Inc.
发明人: Michael Tsirkin , Amnon Ilan
CPC分类号: G06F21/572 , G06F12/0238 , G06F21/602 , G06F21/64 , G06F2212/402
摘要: Systems and methods for verifying firmware before it is loaded to a memory device are presented herein. An amount of available memory remaining in a memory device after firmware is written to the memory device is determined, and padding data having a size equal to the determined amount of remaining available memory is generated and appended to the firmware (e.g., the firmware is padded with the padding data). In this way, there is no room for malicious code or a malicious version of the firmware in the memory device. A processing device may determine a verification value of the padded firmware and store the verification value. The verification value may be a cryptographic hash of the padded firmware or a cryptographic signature of the padded firmware. The padded firmware is then written to the memory device. The firmware may be read from the memory device and verified using the verification value.
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公开(公告)号:US11797683B2
公开(公告)日:2023-10-24
申请号:US17382333
申请日:2021-07-21
发明人: Paul C. Kocher , Pankaj Rohatgi , Joshua M. Jaffe
IPC分类号: G06F21/57 , G06F21/60 , H04L9/08 , H04L9/32 , G06F21/55 , H04L9/00 , G06F12/14 , H04L9/06 , H04L9/16 , G06F9/445 , G06F21/76 , G06F8/71 , H04L9/40 , G06F21/75
CPC分类号: G06F21/575 , G06F8/71 , G06F9/44505 , G06F12/1408 , G06F21/556 , G06F21/602 , G06F21/76 , H04L9/003 , H04L9/0631 , H04L9/085 , H04L9/088 , H04L9/0861 , H04L9/0894 , H04L9/16 , H04L9/3236 , H04L9/3247 , H04L9/3271 , G06F21/755 , G06F2212/402 , G06F2221/034 , G06F2221/2107 , G06F2221/2125 , G06F2221/2145 , H04L9/50 , H04L63/0428 , H04L63/0869 , H04L2209/24 , H04L2209/56 , H04L2463/061
摘要: A method for performing a security chip protocol comprises receiving, by processing hardware of a security chip, a message from a first device as part of performing the security chip protocol. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware determines a path through a key tree based at least in part on the message. The processing hardware derives a validator at least in part from the secret value using a sequence of entropy redistribution operations associated with the path through the key tree. The processing hardware exchanges the validator between the security chip and the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.
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公开(公告)号:US20230283482A1
公开(公告)日:2023-09-07
申请号:US18196266
申请日:2023-05-11
发明人: William Frederick Hingle Kruse , Conor Patrick Cahill , Jeffrey Cicero Canton , Dmitry Frenkel , Harshad Vasant Kulkarni , Colin Watson , Andrew Paul Mikulski
CPC分类号: H04L9/3247 , G06F12/1408 , H04L63/061 , H04L63/126 , G06F2212/402
摘要: A request to add tags (e.g., labels, key-value pairs, or metadata) to resources can be digitally signed by the entity making the request, such that the source can be verified and an authorization determination made for each tag. For a request involving multiple services (or entities) that can each add tags, any tag added by a service can be included in the request and digitally signed by that service. Each service processing the request can also digitally sign the request before forwarding, so that each service signs a version of the request, which includes elements signed by other services earlier in the request chain. When the request is received to a tagging service, the service ensures that every tag was digitally signed by the appropriate authorized entity or service, and validates the signatures to ensure that no data was modified or omitted, before adding the tags to the designated resource(s).
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公开(公告)号:US11720361B2
公开(公告)日:2023-08-08
申请号:US17452271
申请日:2021-10-26
发明人: Andre′ DeHon , Eli Boling
CPC分类号: G06F9/30101 , G06F9/30072 , G06F9/30098 , G06F9/3867 , G06F12/0875 , G06F12/1408 , G06F12/1458 , G06F15/78 , G06F21/52 , G06F21/6218 , G06F2212/1052 , G06F2212/402 , G06F2212/452
摘要: Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture.
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公开(公告)号:US11687264B2
公开(公告)日:2023-06-27
申请号:US15721053
申请日:2017-09-29
申请人: Intel Corporation
发明人: Chih-Jen Chang , Brad Burres , Jose Niell , Dan Biederman , Robert Cone , Pat Wang , Kenneth Keels , Patrick Fleming
IPC分类号: H04L67/63 , G06F3/06 , G06F16/174 , G06F21/57 , G06F21/73 , G06F8/65 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L67/10 , G06F11/30 , G06F9/50 , H01R13/453 , G06F9/48 , G06F9/455 , H05K7/14 , H04L61/5007 , H04L67/75 , H03M7/30 , H03M7/40 , H04L43/08 , H04L47/20 , H04L47/2441 , G06F11/07 , G06F11/34 , G06F7/06 , G06T9/00 , H03M7/42 , H04L12/28 , H04L12/46 , G06F13/16 , G06F21/62 , G06F21/76 , H03K19/173 , H04L9/08 , H04L41/044 , H04L49/104 , H04L43/04 , H04L43/06 , H04L43/0894 , G06F9/38 , G06F12/02 , G06F12/06 , G06T1/20 , G06T1/60 , G06F9/54 , H04L67/1014 , G06F8/656 , G06F8/658 , G06F8/654 , G06F9/4401 , H01R13/631 , H04L47/78 , G06F16/28 , H04Q11/00 , G06F11/14 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L9/40 , G06F15/80
CPC分类号: G06F3/0641 , G06F3/0604 , G06F3/065 , G06F3/067 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/0653 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/45533 , G06F9/4843 , G06F9/4881 , G06F9/5005 , G06F9/505 , G06F9/5038 , G06F9/5044 , G06F9/5083 , G06F9/544 , G06F11/0709 , G06F11/079 , G06F11/0751 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3079 , G06F11/3409 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/453 , H01R13/4536 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/1452 , H05K7/1487 , H05K7/1491 , G06F11/1453 , G06F12/023 , G06F15/80 , G06F16/285 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L47/78 , H04L63/1425 , H04Q11/0005 , H05K7/1447 , H05K7/1492
摘要: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.
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公开(公告)号:US20190121557A1
公开(公告)日:2019-04-25
申请号:US16223162
申请日:2018-12-18
发明人: Jayarama N. Shenoy
CPC分类号: G06F3/0623 , G06F3/0659 , G06F3/0661 , G06F3/0673 , G06F3/0679 , G06F12/1408 , G06F2212/1052 , G06F2212/402
摘要: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.
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公开(公告)号:US20180276392A1
公开(公告)日:2018-09-27
申请号:US15464711
申请日:2017-03-21
申请人: NXP B.V.
IPC分类号: G06F21/60 , G06F12/0891
CPC分类号: G06F21/602 , G06F12/0891 , G06F12/1408 , G06F21/64 , G06F21/74 , G06F21/79 , G06F2212/1021 , G06F2212/1052 , G06F2212/402 , G06F2212/60 , H04L9/0643 , H04L9/0897 , H04L9/3236
摘要: A data processing system having rich execution environment (REE) and a trusted execution environment (TEE) is provided. In the data processing system, an unsecure memory is coupled to the REE and used for storing encrypted data for use in the TEE. The TEE may have a cache for storing the encrypted data after it is decrypted. The data in both the memory and the cache is organized in blocks, and the cache is smaller than the memory. An interpreter is provided in the TEE, along with a service block in the REE, for fetching and decrypting the data to be stored in the cache. The interpreter checks an integrity of the decrypted data using a hash tree having multiple levels. In the event of a cache miss, all blocks of the hash tree in a path from the data block to a root block are retrieved from the memory in one access operation. A method for operating the cache in the data processing system is also provided.
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公开(公告)号:US10085358B2
公开(公告)日:2018-09-25
申请号:US15396646
申请日:2016-12-31
申请人: Intel Corporation
CPC分类号: H04Q11/0005 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0655 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/3887 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F9/544 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F16/9014 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/00 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1442 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/14 , Y02D10/151 , Y02P90/30 , Y04S10/54 , Y10S901/01
摘要: A sled for operation in a corresponding rack of a data center includes a chassis-less circuit board substrate having one or more physical resources coupled to a top side of the chassis-less circuit board and one or more memory devices coupled to a bottom side of the chassis-less circuit board. The sled does not include a housing or chassis and is opened to the local environment. In the illustrative embodiments, the sled may be embodied as a compute sled, an accelerator sled, or a storage sled.
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