公开(公告)号：US20190253810A1

公开(公告)日：2019-08-15

申请号：US16343835

申请日：2017-10-25

申请人： KNOWLES ELECTRONICS, LLC

发明人： Andrzej PAWLOWSKI ,  Christopher Konrad WOLF ,  Niel D. WARREN

IPC分类号： H04R19/04 ,  H04R1/22 ,  G06F13/42 ,  H04R3/06

CPC分类号： H04R19/04 ,  G06F13/42 ,  G06F13/4282 ,  H04R1/222 ,  H04R3/06 ,  Y02D10/14 ,  Y02D10/151

摘要： A method in a transducer assembly having an external-device interface coupled to a communication protocol interface of the transducer assembly. The transducer assembly is configured to convert an input signal having one physical form to an output signal having a different physical form. At least two electrical signals are received on corresponding contacts of the external-device interface of the transducer assembly. A characteristic of at least one of the electrical signals is determined by evaluating a logic transition of the signal. A unique identity assigned to the transducer assembly is determined based on the characteristic.

公开(公告)号：US20190215015A1

公开(公告)日：2019-07-11

申请号：US16357696

申请日：2019-03-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Shinichi KANNO ,  Hironori UCHIKAWA

IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/35 ,  G11C29/52 ,  G06F13/16 ,  H03M13/00 ,  G06F13/40

CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

公开(公告)号：US20190212805A1

公开(公告)日：2019-07-11

申请号：US16357610

申请日：2019-03-19

申请人： MICRON TECHNOLOGY, INC.

发明人： Terry M. Grunzke ,  Ryan G. Fisher

IPC分类号： G06F1/3234

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/14

摘要： Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

公开(公告)号：US20190212767A1

公开(公告)日：2019-07-11

申请号：US16357652

申请日：2019-03-19

申请人： MICRON TECHNOLOGY, INC.

发明人： Yuan He

IPC分类号： G06F1/06 ,  G06F1/3234 ,  G11C11/4076 ,  G11C7/22

CPC分类号： G06F1/06 ,  G06F1/3275 ,  G11C7/222 ,  G11C11/4076 ,  Y02D10/13 ,  Y02D10/14

摘要： Apparatus and methods of reducing dock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part, on the memory command.

公开(公告)号：US20190197009A1

公开(公告)日：2019-06-27

申请号：US16291538

申请日：2019-03-04

申请人： Delta Electronics, Inc.

发明人： Tien-He CHEN ,  Che-Min CHEN

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4282 ,  G06F13/385 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A module comprising a USB Type-C receptacle, a USB Type-C plug and a logic unit is disclosed. A power pin of the receptacle is connected with another power pin of the plug via a switch. A CC pin of the receptacle is connected to ground through a pull-down resistance. Another CC pin of the plug is connected to the logic unit through a pull-up resistance. The module connects with a power source device being a power sink-role in order to receive a source capability of the power source device, then turns on the switch and transforms itself to a power source-role. The module connects to a DRP device afterward being the power source-role to act for the power source device and perform a USB PD communication with the DRP device.

公开(公告)号：US20190171597A1

公开(公告)日：2019-06-06

申请号：US16273621

申请日：2019-02-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JUN HEE YOO ,  JAE GEUN YUN ,  BUB CHUL JEONG ,  DONG SOO KANG ,  KYEO RAE LEE ,  SEONG MIN JO

IPC分类号： G06F13/368 ,  G06F13/40

CPC分类号： G06F13/368 ,  G06F13/1621 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

摘要： A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

公开(公告)号：US20190171385A1

公开(公告)日：2019-06-06

申请号：US16201729

申请日：2018-11-27

申请人： Micron Technology, Inc.

发明人： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00

CPC分类号： G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

公开(公告)号：US20180373451A1

公开(公告)日：2018-12-27

申请号：US16117348

申请日：2018-08-30

申请人： MICRON TECHNOLOGY, INC.

发明人： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC分类号： G06F3/06 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G06F13/28 ,  G06F12/0846 ,  G06F12/0804

CPC分类号： G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

摘要： Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

公开(公告)号：US20180336152A1

公开(公告)日：2018-11-22

申请号：US16048449

申请日：2018-07-30

申请人： Liqid Inc.

发明人： Christopher Long ,  Jason Breakstone

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F11/30 ,  G05B11/01 ,  G06F3/06 ,  G06F11/00 ,  G06F11/14 ,  G06F11/20

CPC分类号： G06F13/4022 ,  G05B11/01 ,  G06F3/0617 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/00 ,  G06F11/1441 ,  G06F11/2015 ,  G06F11/3034 ,  G06F11/3058 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage apparatus is provided. The data storage apparatus includes a plurality of storage drives each comprising a drive Peripheral Component Interconnect Express (PCIe) interface. A PCIe switch circuit is coupled to the drive PCIe interfaces of the plurality of storage drives, and the PCIe switch comprises at least two host PCIe interfaces shared among the plurality of storage drives. The PCIe switch circuit is configured to receive storage operations transferred by more than one host system over the at least two host PCIe interfaces, and transfer the storage operations for delivery to selected ones of the plurality of storage drives.

公开(公告)号：US20180329708A1

公开(公告)日：2018-11-15

申请号：US16042957

申请日：2018-07-23

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith

IPC分类号： G06F9/30 ,  G06F15/80 ,  G06F9/26 ,  G06F12/0806 ,  G06F11/36 ,  G06F9/52 ,  G06F9/46 ,  G06F9/38 ,  G06F15/78 ,  G06F13/42 ,  G06F9/35 ,  G06F9/345 ,  G06F12/1009 ,  G06F9/32 ,  G06F12/0862 ,  G06F9/355 ,  G06F12/0811 ,  G06F12/0875

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.