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公开(公告)号：US11900987B2
公开(公告)日：2024-02-13
申请号：US16951919
申请日：2020-11-18
IPC分类号： G11C7/12 , G11C11/4094 , G11C5/06 , G11C11/4074 , G11C14/00
CPC分类号： G11C11/4094 , G11C5/06 , G11C11/4074 , G11C14/009 , G11C14/0054 , G11C14/0081
摘要： The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.
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公开(公告)号：US20230162785A1
公开(公告)日：2023-05-25
申请号：US17695578
申请日：2022-03-15
发明人： Zheng-Jun LIN , Chin-I SU , Chung-Cheng CHOU , Chia-Fu LEE
IPC分类号： G11C11/419 , G11C11/412 , G11C14/00 , H03K19/20
CPC分类号： G11C11/419 , G11C11/412 , G11C14/009 , H03K19/20 , H03K19/21
摘要： A memory device including a static random-access memory that includes two cross-coupled inverters and an access transistor having a gate connected to a word line. The memory device further includes one or more logic gates electrically coupled to the static random-access memory, and a non-volatile memory electrically coupled to the static random-access memory and configured to store data and be read using the static random-access memory, wherein the non-volatile memory is connected on one side to the access transistor and on another side to the two cross-coupled inverters.
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公开(公告)号：US20190171385A1
公开(公告)日：2019-06-06
申请号：US16201729
申请日：2018-11-27
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
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4.发明授权公开(公告)号：US10082976B2
公开(公告)日：2018-09-25
申请号：US14921877
申请日：2015-10-23
发明人： Gerald Barkley , Poorna Kale
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0679 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C14/009 , G11C16/10 , G11C16/102 , G11C16/20 , G11C16/30
摘要： Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.
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公开(公告)号：US20180225205A1
公开(公告)日：2018-08-09
申请号：US15633383
申请日：2017-06-26
申请人： R. Joseph Trojan
发明人： R. Joseph Trojan
IPC分类号： G06F12/0811 , G06F12/0897 , G11C11/406 , G11C14/00 , G06F12/0895
CPC分类号： G06F12/0811 , A47J43/046 , A47J43/0716 , G06F12/0895 , G06F12/0897 , G06F2212/2024 , G06F2212/205 , G11C11/40615 , G11C14/009 , Y02D10/13
摘要： A vacuum blender having a vessel, a motor base containing a motor having a motor drive shaft, a blade holder having a blade with a blade shaft for engaging the motor drive shaft, and a fan connected to the motor drive shaft. The blender includes a conduit system for the passage of air from the vessel to an area in proximity to the fan before passing to the outside of the motor base. The conduit system is connected to a valve system, preferably including a three way valve or Venturi valve. The fan and blade are capable of being selectively actuated using a gear or clutch system, preferably operated by firmware. The invention is capable of evacuating air from the vessel before blending of the food contents occurs.
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公开(公告)号：US20180174644A1
公开(公告)日：2018-06-21
申请号：US15833802
申请日：2017-12-06
IPC分类号： G11C11/417 , G11C13/00
CPC分类号： G11C11/417 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/4125 , G11C11/419 , G11C13/0038 , G11C14/0081 , G11C14/009
摘要： A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.
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公开(公告)号：US09922689B2
公开(公告)日：2018-03-20
申请号：US15089370
申请日：2016-04-01
申请人： Intel Corporation
CPC分类号： G11C7/1072 , G06F9/4401 , G06F12/10 , G06F13/16 , G06F13/1694 , G06F2212/1044 , G11C14/0063 , G11C14/0081 , G11C14/009
摘要： Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.
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公开(公告)号：US09921761B2
公开(公告)日：2018-03-20
申请号：US15343576
申请日：2016-11-04
发明人： Radoslav Danilak
IPC分类号： G11C11/34 , G06F3/06 , G11C16/34 , G06F12/02 , G11C29/04 , G06F11/10 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/52 , G11C14/00 , G11C17/00
CPC分类号： G06F3/0616 , G06F3/0608 , G06F3/0631 , G06F3/064 , G06F3/0649 , G06F3/0652 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F11/1072 , G06F12/023 , G06F12/0246 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211 , G11C14/009 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/349 , G11C16/3495 , G11C17/00 , G11C29/04 , G11C29/52
摘要： The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.
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公开(公告)号：US20170352403A1
公开(公告)日：2017-12-07
申请号：US15214580
申请日：2016-07-20
发明人： Jaesoo LEE , Myoungsoo JUNG , Gyuyoung PARK
IPC分类号： G11C11/406 , G06F3/06 , G11C14/00
CPC分类号： G11C11/40607 , G06F3/0611 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G11C7/1042 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009
摘要： A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions is provided. A write request that request a data write to the memory device and a read request which request a data read from the memory device are inserted to a request queue. A scheduler, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition. The second partition is a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.
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公开(公告)号：US20170287532A1
公开(公告)日：2017-10-05
申请号：US15089370
申请日：2016-04-01
申请人： Intel Corporation
CPC分类号： G11C7/1072 , G06F9/4401 , G06F12/10 , G06F13/16 , G06F13/1694 , G06F2212/1044 , G11C14/0063 , G11C14/0081 , G11C14/009
摘要： Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.
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