公开(公告)号：US20230207036A1

公开(公告)日：2023-06-29

申请号：US18179434

申请日：2023-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adolf Baumann ,  Mark Jung

IPC: G11C29/36 ,  G11C14/00

CPC classification number: G11C29/36 ,  G11C14/0063 ,  G11C5/148 ,  G11C2029/3602

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

公开(公告)号：US20190122739A1

公开(公告)日：2019-04-25

申请号：US16222160

申请日：2018-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Rainer Bonitz

IPC: G11C16/34 ,  G11C16/08

CPC classification number: G11C16/3418 ,  G11C14/0063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/225 ,  G11C16/26 ,  G11C16/30

Abstract: Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

公开(公告)号：US20180336948A1

公开(公告)日：2018-11-22

申请号：US15981920

申请日：2018-05-17

Applicant: Aspiring Sky Co. Limited

Inventor： Zhijiong LUO ,  Shu WANG ,  Xiaoming JIN

IPC: G11C14/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C14/0063 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/005 ,  G11C16/04 ,  G11C16/10 ,  G11C16/107 ,  G11C16/20 ,  G11C16/26 ,  G11C16/32

Abstract: A memory system may include one or more hybrid fast memory blocks with m-bit fast volatile random access memory (RAM) cells and N×m bit non-volatile memory (NVM) cells. The memory system may also include one or more other memory blocks with NVM cells. The fast flash memory may buffer the NVM data improving access speed. The different memory blocks may utilize a single, unified interface to communicate with other devices/circuits. The unified interface may be a parallel interface (e.g., flash memory/SRAM combinations), or the unified interface may be a pipeline interface (e.g., system on a chip “SOC” implementations) supporting fast memory read/write operations.

公开(公告)号：US20180166139A1

公开(公告)日：2018-06-14

申请号：US15891284

申请日：2018-02-07

Applicant: NEO Semiconductor, Inc.

Inventor： Fu-Chang Hsu

IPC: G11C14/00 ,  G11C11/00 ,  G11C11/419 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C14/0063 ,  G11C11/005 ,  G11C11/419 ,  G11C16/0483 ,  G11C16/10

Abstract: A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

公开(公告)号：US20180081802A1

公开(公告)日：2018-03-22

申请号：US15704011

申请日：2017-09-14

Applicant: Aspiring Sky Co. Limited

Inventor： Zhijiong LUO ,  Shu WANG ,  Xiaoming JIN

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16

CPC classification number: G11C11/4085 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/7203 ,  G11C5/025 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Technologies are generally described herein for a hybrid non-volatile memory structure that includes a number of SRAM buffers. SRAM access times may be achieved for non-volatile read/write operations by performing access queue buffered read/write operations first. The SRAM buffer may be shareable as a system SRAM. In other examples, a hybrid non-volatile memory according to some embodiments may include a high speed block and a high endurance block to store different types of data with different access needs. The hybrid non-volatile memory may also include a normal block to store the data which is non-frequently changed.

公开(公告)号：US09728248B2

公开(公告)日：2017-08-08

申请号：US14657914

申请日：2015-03-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  H01L27/11

CPC classification number: G11C11/41 ,  G11C11/4125 ,  G11C14/0054 ,  G11C14/0063 ,  G11C16/0416 ,  H01L23/5226 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US09653164B2

公开(公告)日：2017-05-16

申请号：US14656832

申请日：2015-03-13

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Cheong Min Hong ,  Laureen H. Parker

IPC: G11C14/00 ,  H01L29/51 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: G11C14/0063 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/823462 ,  H01L27/11524 ,  H01L27/11534 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.

公开(公告)号：US09472247B2

公开(公告)日：2016-10-18

申请号：US14621521

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Cheng-Hsiung Kuo ,  Gu-Huan Li ,  Jih-Chen Wang ,  Chung-Chieh Chen

IPC: G11C7/10 ,  G11C29/00 ,  G11C7/22 ,  G11C14/00

CPC classification number: G11C7/106 ,  G11C7/22 ,  G11C14/0054 ,  G11C14/0063 ,  G11C16/18 ,  G11C29/00 ,  G11C29/1201 ,  G11C29/48

Abstract: A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.

Abstract translation: 存储器包括第一存储单元，第二存储单元，锁存单元和开关单元。 锁存单元具有真实节点和补码节点。 开关单元响应于第一控制信号和第二控制信号，并且被配置为响应于第一控制信号将第一存储器单元连接到真实节点并且将第二存储器单元与补码节点断开连接，并且连接 所述第二存储器单元发送到所述补码节点并且响应于所述第二控制信号而将所述第一存储器单元与所述真实节点断开。 还公开了包括存储器的半导体器件。 还公开了一种用于测试存储器的方法。

公开(公告)号：US20160111159A1

公开(公告)日：2016-04-21

申请号：US14886663

申请日：2015-10-19

Applicant: Cypress Semiconductor Corporation

Inventor： Joseph S. Tandingan ,  Jayant Ashokkumar ,  David Still ,  Jesse J. Siman

IPC: G11C14/00 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C11/419 ,  G11C14/0063 ,  G11C16/0466

Abstract: A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract translation: 提供了包括nvSRAM单元阵列的存储器及其操作方法。 每个nvSRAM单元包括易失性电荷存储电路，以及非易失性电荷存储电路，其包括正好一个非易失性存储器（NVM）元件，耦合到NVM元件的第一晶体管，通过该元件将数据真实耦合到易失性电荷存储电路 耦合到所述NVM元件的第二晶体管，通过所述第二晶体管将所述数据的互补件耦合到所述易失性电荷存储电路;以及第三晶体管，所述NVM元件通过所述第三晶体管耦合到正电压电源线（VCCT）。 在一个实施例中，第一晶体管耦合到NVM元件的第一节点，第二晶体管耦合到NVM元件的第二节点，第三晶体管耦合在第一节点和VCCT之间。 还公开了其他实施例。

公开(公告)号：US09245627B2

公开(公告)日：2016-01-26

申请号：US14296014

申请日：2014-06-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00 ,  G11C16/04 ,  G11C5/02 ,  G11C16/20 ,  G11C11/404

CPC classification number: G11C16/0408 ,  G11C11/404 ,  G11C14/0018 ,  G11C14/0063 ,  G11C16/20

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract translation: 存储器件包括具有基本SRAM型单元的存储单元和耦合在供电端和基本SRAM型单元之间的基本模块。 基本模块具有包括浮栅晶体管的单个非易失性EEPROM单元存储单元。 基本模块还具有可控制的互连级，其可以由存储器单元外部的控制信号控制。 非易失性基本存储单元和可控互连级彼此连接。 当存储在基本SRAM型单元中的数据项被编程到非易失性单元中时，非易失性存储单元的浮置栅晶体管被控制为截止。