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    Multiple accelerators for neural network
    1.
    发明授权
    Multiple accelerators for neural network 有权

    公开(公告)号：US11568219B2

    公开(公告)日：2023-01-31

    申请号：US15931771

    申请日：2020-05-14

    Applicant: Aspiring Sky Co. Limited

    Inventor： Yujie Wen ,  Zhijiong Luo

    IPC: G06N3/063 ,  G06F9/50

    Abstract: Technologies are described for multiple accelerators for a neural network, and methods thereof. In an example implementation, a neural network can be mapped to a system comprising a control unit and multiple accelerators, where the controller unit controls each accelerator's behavior, sends data to and receives data from each accelerator through the interconnections. Sub-networks may be created by grouping several network layers or dividing a network layer into multiple sub-layers depending on data to be processed and memory capacity of each accelerator. Accelerators have internal storage, thus, do not require external memory.

    NONVOLATILE MEMORY STRUCTURES WITH DRAM
    2.
    发明申请
    NONVOLATILE MEMORY STRUCTURES WITH DRAM 有权

    公开(公告)号：US20210134353A1

    公开(公告)日：2021-05-06

    申请号：US17144340

    申请日：2021-01-08

    Applicant: Aspiring Sky Co. Limited

    Inventor： Zhijiong LUO ,  Xuntong ZHAO

    IPC: G11C11/408 ,  G11C8/10 ,  G11C14/00 ,  G11C5/02 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/419 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

    Abstract: Technologies for a three-dimensional (3D) multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.

    Circuit for neural network convolutional calculation of variable feature and kernel sizes
    7.
    发明授权
    Circuit for neural network convolutional calculation of variable feature and kernel sizes 有权

    公开(公告)号：US11514136B2

    公开(公告)日：2022-11-29

    申请号：US15931730

    申请日：2020-05-14

    Applicant: Aspiring Sky Co. Limited

    Inventor： Yujie Wen ,  Zhijiong Luo

    IPC: G06F17/15 ,  G06F17/16

    Abstract: A circuit for performing parallel convolutional computation for features and kernels of variable sizes may receive inputs of an m×n matrix of feature data, an m×n matrix of convolution data, and a (2m−1)×(2n−1) matrix of kernel data. A feature manager of the circuit may hold m rows of n data buffers storing the input feature data and rotating values between rows during one restricted convolution calculation. A kernel manager of the circuit may hold a (2m−1)×(2n−1) matrix of data buffers storing the input kernel data in the buffers and cyclically rotating values in upwards, downwards, leftwards and rightwards directions for different restricted convolution calculations. A row convolution engine of the circuit may hold m row convolution processors, each storing and updating input convolution data by multiplication-and-accumulation (MAC) operations on its input feature and kernel data rows. The circuit produces accumulated convolutional data.

    Memory structure for artificial intelligence (AI) applications
    8.
    发明授权
    Memory structure for artificial intelligence (AI) applications 有权

    公开(公告)号：US11270748B2

    公开(公告)日：2022-03-08

    申请号：US16782157

    申请日：2020-02-05

    Applicant: Aspiring Sky Co., Limited

    Inventor： Zhijiong Luo ,  Xuntong Zhao

    IPC: G11C11/22 ,  G11C11/16 ,  G11C14/00 ,  G11C13/00 ,  G06N20/00

    Abstract: Technologies for various memory structures for artificial intelligence (AI) applications and methods thereof are described. An XNOR circuit along with a sense amplifier may be combined with an array (or multiple arrays) of memory such as non-volatile memory (NVM) or an NVM, SRAM combination to perform an XNOR operation on the data read from the memory. Various versions may include different connections allowing simplification of circuitry or timing. In some examples, memory array may include programmable resistor/switch device combinations, or multiple columns connected to a single XNOR+SA circuit.

    Re-configurable non-volatile memory structures and systems
    10.
    发明授权
    Re-configurable non-volatile memory structures and systems 有权

    公开(公告)号：US10402342B2

    公开(公告)日：2019-09-03

    申请号：US15787665

    申请日：2017-10-18

    Applicant: Aspiring Sky Co., Limited

    Inventor： Zhijiong Luo ,  Xiaoming Jin ,  Shu Wang

    IPC: G06F12/1009 ,  G06F3/06 ,  H03K19/177 ,  G11C16/04 ,  G11C7/10

    Abstract: Technologies are described for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.

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