公开(公告)号：US12112794B2

公开(公告)日：2024-10-08

申请号：US18297605

申请日：2023-04-08

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C7/14 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/56 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094

CPC分类号： G11C11/4096 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4091 ,  G11C11/565 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094 ,  G11C2207/2254

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

公开(公告)号：US12108682B2

公开(公告)日：2024-10-01

申请号：US17386455

申请日：2021-07-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Baolei Wu ,  Xiaoguang Wang ,  Yulei Wu

IPC分类号： H10N50/10 ,  G11C7/18 ,  G11C8/14 ,  H01L23/528 ,  H10B61/00 ,  H10N50/80

CPC分类号： H10N50/10 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/80

摘要： Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.

公开(公告)号：US12075619B2

公开(公告)日：2024-08-27

申请号：US17193383

申请日：2021-03-05

申请人： SK hynix Inc.

发明人： Nam Jae Lee

IPC分类号： H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC分类号： H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

摘要： A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

公开(公告)号：US12063795B2

公开(公告)日：2024-08-13

申请号：US17542886

申请日：2021-12-06

申请人： SK hynix Inc.

发明人： Jae Hyun Han

IPC分类号： H10B63/00 ,  G11C7/18 ,  G11C8/14 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  G11C7/18 ,  G11C8/14 ,  H10N70/25 ,  H10N70/8833

摘要： A semiconductor device includes a substrate, a first bit line disposed on the substrate, a first tunnel insulation layer disposed on the first bit line, a variable resistance structure disposed on the first tunnel insulation layer and having a pillar structure, a second tunnel insulation layer disposed on an upper surface of the variable resistance structure, a second bit line disposed on the second tunnel insulation layer, a barrier insulation layer disposed on a sidewall surface of the variable resistance structure, and a word line disposed on the barrier insulation layer. A dielectric constant of the barrier insulation layer is greater than a dielectric constant of each of the first and second tunnel insulation layers.

公开(公告)号：US20240250007A1

公开(公告)日：2024-07-25

申请号：US18358644

申请日：2023-07-25

申请人： SanDisk Technologies LLC

发明人： Hiroki Yabe

IPC分类号： H01L23/498 ,  G11C7/18 ,  G11C16/28 ,  H01L23/00 ,  H01L25/065 ,  H10B43/35

CPC分类号： H01L23/49822 ,  G11C7/18 ,  G11C16/28 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H10B43/35 ,  H01L2224/08055 ,  H01L2224/08145 ,  H01L2224/16055 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1438 ,  H01L2924/1815

摘要： Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

公开(公告)号：US12022658B2

公开(公告)日：2024-06-25

申请号：US18356064

申请日：2023-07-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kwangyoung Jung ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC分类号： H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

摘要： A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

公开(公告)号：US12014799B2

公开(公告)日：2024-06-18

申请号：US17842766

申请日：2022-06-16

申请人： Winbond Electronics Corp.

发明人： Naohito Morozumi

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC分类号： G11C7/18 ,  G11C7/1039 ,  G11C7/12

摘要： The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).

公开(公告)号：US11980028B2

公开(公告)日：2024-05-07

申请号：US17343330

申请日：2021-06-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Geunwon Lim ,  Minjun Kang ,  Byunggon Park ,  Joongshik Shin

IPC分类号： H10B43/27 ,  G11C7/18 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC分类号： H10B41/40 ,  G11C7/18 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

摘要： A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.

公开(公告)号：US20240147738A1

公开(公告)日：2024-05-02

申请号：US18404103

申请日：2024-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-I Wu ,  Yu-Ming Lin

IPC分类号： H10B63/00 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H01L29/78 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/34 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H01L29/78391 ,  H10N70/061 ,  H10N70/253 ,  H10N70/8265 ,  H10N70/841

摘要： A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

公开(公告)号：US20240105241A1

公开(公告)日：2024-03-28

申请号：US18170426

申请日：2023-02-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yu Lin ,  Yi-Hsin Nien ,  Hidehiro Fujiwara ,  Yen-Huei Chen

IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C7/222

摘要： Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.