公开(公告)号：US12014770B2

公开(公告)日：2024-06-18

申请号：US17649342

申请日：2022-01-28

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C7/14 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/56 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094

CPC分类号： G11C11/4096 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4091 ,  G11C11/565 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094 ,  G11C2207/2254

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

公开(公告)号：US10796749B2

公开(公告)日：2020-10-06

申请号：US16543331

申请日：2019-08-16

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C16/06 ,  G11C11/4096 ,  G11C11/4091 ,  G11C5/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/56 ,  G11C7/14 ,  G11C11/404 ,  G11C7/06 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

公开(公告)号：US20240127884A1

公开(公告)日：2024-04-18

申请号：US18397533

申请日：2023-12-27

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C11/4096 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/56 ,  G11C16/30

CPC分类号： G11C11/4096 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4091 ,  G11C11/565 ,  G11C16/30 ,  G11C11/4094

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

公开(公告)号：US20210082490A1

公开(公告)日：2021-03-18

申请号：US17105927

申请日：2020-11-27

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C5/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/56 ,  G11C7/14 ,  G11C11/404 ,  G11C7/06 ,  G11C16/30

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

公开(公告)号：US11501826B2

公开(公告)日：2022-11-15

申请号：US17105927

申请日：2020-11-27

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C16/30 ,  G11C11/4096 ,  G11C5/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/56 ,  G11C7/14 ,  G11C11/404 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C8/16 ,  G11C11/405

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

公开(公告)号：US11049553B2

公开(公告)日：2021-06-29

申请号：US16802902

申请日：2020-02-27

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C11/00 ,  G11C11/4096 ,  G11C11/4091 ,  G11C5/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/56 ,  G11C7/14 ,  G11C11/404 ,  G11C7/06 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

公开(公告)号：US20190378562A1

公开(公告)日：2019-12-12

申请号：US16543331

申请日：2019-08-16

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C5/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/56 ,  G11C7/14 ,  G11C7/06 ,  G11C16/30

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

公开(公告)号：US20190139595A1

公开(公告)日：2019-05-09

申请号：US16242419

申请日：2019-01-08

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C11/4091 ,  G11C5/06 ,  G11C7/18 ,  G11C7/08 ,  G11C11/4096 ,  G11C7/14 ,  G11C11/56

摘要： Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

公开(公告)号：US10236053B1

公开(公告)日：2019-03-19

申请号：US16040442

申请日：2018-07-19

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C11/40 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/56 ,  G11C7/14 ,  G11C7/08 ,  G11C7/18 ,  G11C5/06

摘要： Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

公开(公告)号：US12112794B2

公开(公告)日：2024-10-08

申请号：US18297605

申请日：2023-04-08

申请人： R&D 3 LLC

发明人： Ravindraraj Ramaraju

IPC分类号： G11C7/14 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/56 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094

CPC分类号： G11C11/4096 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4091 ,  G11C11/565 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094 ,  G11C2207/2254

摘要： The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.