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    BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    2.
    发明公开
    BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20240339153A1

    公开(公告)日：2024-10-10

    申请号：US18746974

    申请日：2024-06-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hoseok LEE ,  Sunyoung KIM ,  Younghun SEO

    IPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    摘要： A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

    Compute in memory system
    5.
    发明授权
    Compute in memory system 有权

    公开(公告)号：US12073869B2

    公开(公告)日：2024-08-27

    申请号：US17734701

    申请日：2022-05-02

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Mahmut Sinangil

    IPC分类号： G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  H03M1/80

    CPC分类号： G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  H03M1/802

    摘要： A computing device in some examples includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.

    LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES
    6.
    发明公开
    LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES 审中-公开

    公开(公告)号：US20240284659A1

    公开(公告)日：2024-08-22

    申请号：US18440460

    申请日：2024-02-13

    申请人： Micron Technology, Inc.

    发明人： Lorenzo Fratin ,  Fabio Pellizzer

    IPC分类号： H10B12/00 ,  G11C11/408 ,  G11C11/4094

    CPC分类号： H10B12/485 ,  G11C11/4085 ,  G11C11/4094 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

    摘要： Methods, systems, and devices for lateral split digit line memory architectures are described. A memory array may include a first set of word line plates separated from a second set of word line plates by a pillar (e.g., that is configured as a digit line) that interact with the first and second set of word line plates. Further, the memory array may include a set of dielectric piers that are positioned between the pillars, where each dielectric pier contacts a first pillar and a second pillar. Additionally, the memory array may include a set of storage elements and a set of digit lines that are each coupled with a word line plate, a pillar, and a dielectric material that is positioned between each first and second pillar of the pairs of pillars.

    PRE-CHARGE VOLTAGE GENERATION CIRCUIT FOR RANDOM MEMORY AND RANDOM MEMORY
    9.
    发明公开
    PRE-CHARGE VOLTAGE GENERATION CIRCUIT FOR RANDOM MEMORY AND RANDOM MEMORY 审中-公开

    公开(公告)号：US20240257859A1

    公开(公告)日：2024-08-01

    申请号：US18234881

    申请日：2023-08-17

    申请人： GigaDevice Semiconductor Inc.

    发明人： Meifeng WANG ,  Miaomiao WU

    IPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    CPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    摘要： Pre-charge voltage generation circuit for a random memory and a random memory are provided. The pre-charge voltage generation circuit is configured to selectively provide a pre-charge voltage and includes: a voltage generation module, configured to generate a first voltage and a second voltage, wherein either of the first voltage and the second voltage serves as the pre-charge voltage, the first voltage is greater than the second voltage; a selection module, coupled to the voltage generation module, configured to select and output the second voltage as the common end voltage of the storage capacitor of the random memory in response to an operation command being a write command, and configured to select and output the first voltage as the common end voltage in response to the operation command being a read command.

    Bit line sense amplifier and semiconductor memory device having the same
    10.
    发明授权
    Bit line sense amplifier and semiconductor memory device having the same 有权

    公开(公告)号：US12051461B2

    公开(公告)日：2024-07-30

    申请号：US17748357

    申请日：2022-05-19

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hoseok Lee ,  Sunyoung Kim ,  Younghun Seo

    IPC分类号： G11C11/40 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    摘要： A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.