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    INTEGRATED CIRCUIT DEVICE
    1.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240304661A1

    公开(公告)日：2024-09-12

    申请号：US18598552

    申请日：2024-03-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gina Lee ,  Seil Oh ,  Inseok Baek ,  Changsik Yoo

    IPC: H10B12/00

    CPC classification number: H01L28/90 ,  H10B12/30 ,  H10B12/50

    Abstract: An integrated circuit device includes a substrate including a cell array region and a peripheral circuit region, a first ion implantation region located in an upper portion of the substrate in the peripheral circuit region, the first ion implantation region having a plurality of line trenches that extend in a first horizontal direction and cross the first ion implantation region, a plurality of lower capacitor dielectric films with each lower capacitor dielectric film configured to respectively cover inner walls of a respective line trench, a plurality of buried conductive lines that each partially fill a respective line trench and that are each respectively disposed on a respective lower capacitor dielectric film, a plurality of first lower capacitor contacts that are each in contact with a respective buried conductive line, and a plurality of second lower capacitor contacts that are in contact with the first ion implantation region.

    BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    3.
    发明申请
    BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250085858A1

    公开(公告)日：2025-03-13

    申请号：US18591238

    申请日：2024-02-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donggeon Kim ,  Myeongsik Ryu ,  Bokyeon Won ,  Seokjae Lee ,  Daehyeon Kwon ,  Kyoungmin Kim ,  Inseok Baek ,  Selyung Yoon

    IPC: G06F3/06

    Abstract: A bit-line sense amplifier includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer. The amplifying circuit is connected to a bit-line and a complementary bit-line, senses a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjusts a voltage of a sensing bit-line and a complementary sensing bit-line based on the voltage difference. The equalizer is connected to the sensing bit-line, and equalizes the bit-line and the complementary bit-line to a precharge voltage, based on an equalizing signal. The equalizer includes an equalizing transistor that has a source, a gate configured to receive the equalizing signal, and a drain. The source of the equalizing transistor is connected to a wiring structure through a direct contact, and the wiring structure is configured to receive the precharge voltage.

    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT
    6.
    发明申请
    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT 有权

    公开(公告)号：US20220406361A1

    公开(公告)日：2022-12-22

    申请号：US17828200

    申请日：2022-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inseok Baek ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Seokjae Lee

    IPC: G11C11/408

    Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

    Memory device having sub wordline driver
    7.
    发明授权
    Memory device having sub wordline driver 有权

    公开(公告)号：US12106795B2

    公开(公告)日：2024-10-01

    申请号：US17724006

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeongsik Ryu ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Sangwook Park ,  Inseok Baek

    IPC: G11C11/408

    CPC classification number: G11C11/4085

    Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

    TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT
    8.
    发明公开
    TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT 审中-公开

    公开(公告)号：US20240178291A1

    公开(公告)日：2024-05-30

    申请号：US18431628

    申请日：2024-02-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byunghoon Cho ,  Inseok Baek ,  Hyeonok Jung ,  Beomyong Hwang

    IPC: H01L29/423 ,  H01L29/10

    CPC classification number: H01L29/4238 ,  H01L29/1095

    Abstract: A transistor with a shared gate structure includes an active area and a gate. The active area has a body extending in a first direction on a substrate, and a protrusion extending in a second direction perpendicular to the first direction from a central portion of the body in the first direction. The gate is arranged above the active area to overlap a channel area of the active area, and has an inverted pi (II) structure that, from a plan view, surrounds on three sides but does not cover a portion of the active area that includes two corner portions of the active area. The active area is divided into a first active area and a second active area by a separation area extending in the second direction and separating the body and a portion of the protrusion. The protrusion is divided into a first portion separated into two sub-portions by the separation area and a second portion, wherein the first portion is between the body and the second portion in the second direction. Opposite ends of the body in the first direction corresponding to two drain areas, the second portion of the protrusion corresponding to a common source area, and the gate constitute two transistors, wherein the two transistors share the gate.

    Transistor unit including shared gate structure, and sub-word line driver and semiconductor device based on the same transistor unit
    9.
    发明授权
    Transistor unit including shared gate structure, and sub-word line driver and semiconductor device based on the same transistor unit 有权

    公开(公告)号：US11929414B2

    公开(公告)日：2024-03-12

    申请号：US17361890

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byunghoon Cho ,  Inseok Baek ,  Hyeonok Jung ,  Beomyong Hwang

    IPC: H01L29/423 ,  H01L29/10

    CPC classification number: H01L29/4238 ,  H01L29/1095

    Abstract: A transistor with a shared gate structure includes an active area and a gate. The active area has a body extending in a first direction on a substrate, and a protrusion extending in a second direction perpendicular to the first direction from a central portion of the body in the first direction. The gate is arranged above the active area to overlap a channel area of the active area, and has an inverted pi () structure that, from a plan view, surrounds on three sides but does not cover a portion of the active area that includes two corner portions of the active area. The active area is divided into a first active area and a second active area by a separation area extending in the second direction and separating the body and a portion of the protrusion. The protrusion is divided into a first portion separated into two sub-portions by the separation area and a second portion, wherein the first portion is between the body and the second portion in the second direction. Opposite ends of the body in the first direction corresponding to two drain areas, the second portion of the protrusion corresponding to a common source area, and the gate constitute two transistors, wherein the two transistors share the gate.

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