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    BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    1.
    发明申请
    BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250085858A1

    公开(公告)日：2025-03-13

    申请号：US18591238

    申请日：2024-02-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donggeon Kim ,  Myeongsik Ryu ,  Bokyeon Won ,  Seokjae Lee ,  Daehyeon Kwon ,  Kyoungmin Kim ,  Inseok Baek ,  Selyung Yoon

    IPC: G06F3/06

    Abstract: A bit-line sense amplifier includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer. The amplifying circuit is connected to a bit-line and a complementary bit-line, senses a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjusts a voltage of a sensing bit-line and a complementary sensing bit-line based on the voltage difference. The equalizer is connected to the sensing bit-line, and equalizes the bit-line and the complementary bit-line to a precharge voltage, based on an equalizing signal. The equalizer includes an equalizing transistor that has a source, a gate configured to receive the equalizing signal, and a drain. The source of the equalizing transistor is connected to a wiring structure through a direct contact, and the wiring structure is configured to receive the precharge voltage.

    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT
    2.
    发明申请
    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT 有权

    公开(公告)号：US20220406361A1

    公开(公告)日：2022-12-22

    申请号：US17828200

    申请日：2022-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inseok Baek ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Seokjae Lee

    IPC: G11C11/408

    Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

    Integrated circuit devices
    3.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US11437089B2

    公开(公告)日：2022-09-06

    申请号：US17245334

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

    IPC: G11C11/4091 ,  H01L27/108

    Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20240395753A1

    公开(公告)日：2024-11-28

    申请号：US18584876

    申请日：2024-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bong geun Choi ,  Jisuk Kwon ,  Seokjae Lee

    IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

    Abstract: A semiconductor memory device includes a memory cell array, first to fourth I/O pads under the memory cell array and configured to connect with an external device, and first to fourth I/O driving modules between the memory cell array and the first to fourth I/O pads and configured to drive the first to fourth I/O pads, respectively. In a plan view, the first and second I/O driving modules are disposed symmetrically with respect to a first line extending in a first direction, the third and fourth I/O driving modules are disposed symmetrically with respect to the first line, the first and third I/O driving modules are disposed symmetrically with respect to a second line extending in a second direction crossing the first direction, and the second and fourth I/O driving modules are disposed symmetrically with respect to the second line.

    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
    6.
    发明申请
    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME 有权

    公开(公告)号：US20220406360A1

    公开(公告)日：2022-12-22

    申请号：US17685849

    申请日：2022-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

    IPC: G11C11/408 ,  H01L27/108

    Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

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