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    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT
    1.
    发明申请
    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT 有权

    公开(公告)号：US20220406361A1

    公开(公告)日：2022-12-22

    申请号：US17828200

    申请日：2022-05-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Inseok Baek ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Seokjae Lee

    IPC分类号： G11C11/408

    摘要： A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

    Integrated circuit devices
    2.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US11437089B2

    公开(公告)日：2022-09-06

    申请号：US17245334

    申请日：2021-04-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

    IPC分类号： G11C11/4091 ,  H01L27/108

    摘要： An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
    4.
    发明申请
    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME 有权

    公开(公告)号：US20220406360A1

    公开(公告)日：2022-12-22

    申请号：US17685849

    申请日：2022-03-03

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

    IPC分类号： G11C11/408 ,  H01L27/108

    摘要： A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.