公开(公告)号：US20240159827A1

公开(公告)日：2024-05-16

申请号：US18506435

申请日：2023-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaecheol Lee ,  Heeyeon Lim ,  Taeheon Lee ,  Doecook Kim ,  Taesung Kang

IPC: G01R31/317 ,  G01R31/3183

CPC classification number: G01R31/31718 ,  G01R31/31713 ,  G01R31/3183

Abstract: A method of generating a fuse configuration for trimming a circuit includes evaluating characteristics, corresponding to each of a plurality of fuse configurations, of the circuit trimmed based on the plurality of fuse configurations respectively, selecting at least one fuse configuration from among the plurality of fuse configurations, based on a result of the evaluating the characteristics of the circuit, calculating a contribution information by calculating a degree of influence of fuse data of each of the plurality of fuse configurations to the characteristics of the circuit, based on the plurality of fuse configurations and the characteristics, and generating at least one new fuse configuration, based on the selected at least one fuse configuration and the contribution information.

公开(公告)号：US11437089B2

公开(公告)日：2022-09-06

申请号：US17245334

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

IPC: G11C11/4091 ,  H01L27/108

Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.