公开(公告)号：US20250159868A1

公开(公告)日：2025-05-15

申请号：US18783044

申请日：2024-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Selyung Yoon ,  Daehyeon Kwon ,  Donggeon Kim ,  Bok-Yeon Won

IPC: H10B12/00 ,  H01L23/522

Abstract: A semiconductor device includes a substrate, a transistor on the substrate, a bit line structure electrically connected to the transistor, a channel layer on the bit line structure, a gate structure intersecting the bit line structure, a first conductive line electrically connecting the transistor and the bit line structure, an upper shield line overlapping the first conductive line, and side shield lines spaced apart from each other with the first conductive line interposed therebetween. The upper shield line and the side shield lines are electrically separated from the first conductive line and the bit line structure.

公开(公告)号：US20250124974A1

公开(公告)日：2025-04-17

申请号：US18618567

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyeon KWON ,  Donggeon Kim ,  Bokyeon Won ,  Selyung Yoon

IPC: G11C11/4097 ,  G11C5/06 ,  G11C11/4091

Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.

公开(公告)号：US20250085858A1

公开(公告)日：2025-03-13

申请号：US18591238

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donggeon Kim ,  Myeongsik Ryu ,  Bokyeon Won ,  Seokjae Lee ,  Daehyeon Kwon ,  Kyoungmin Kim ,  Inseok Baek ,  Selyung Yoon

IPC: G06F3/06

Abstract: A bit-line sense amplifier includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer. The amplifying circuit is connected to a bit-line and a complementary bit-line, senses a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjusts a voltage of a sensing bit-line and a complementary sensing bit-line based on the voltage difference. The equalizer is connected to the sensing bit-line, and equalizes the bit-line and the complementary bit-line to a precharge voltage, based on an equalizing signal. The equalizer includes an equalizing transistor that has a source, a gate configured to receive the equalizing signal, and a drain. The source of the equalizing transistor is connected to a wiring structure through a direct contact, and the wiring structure is configured to receive the precharge voltage.