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公开(公告)号:US11922992B2
公开(公告)日:2024-03-05
申请号:US17828200
申请日:2022-05-31
发明人: Inseok Baek , Bokyeon Won , Kyoungmin Kim , Donggeon Kim , Myeongsik Ryu , Sangwook Park , Seokjae Lee
IPC分类号: G11C16/08 , G11C11/408 , G11C16/10 , G11C16/16
CPC分类号: G11C11/4085 , G11C16/08 , G11C16/10 , G11C16/16
摘要: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.
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公开(公告)号:US11437089B2
公开(公告)日:2022-09-06
申请号:US17245334
申请日:2021-04-30
发明人: Taesung Kang , Youngkyu Lee , Kyoungmin Kim , Ilgweon Kim , Bokyeon Won , Seokjae Lee , Sungho Jang , Joon Han
IPC分类号: G11C11/4091 , H01L27/108
摘要: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.
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公开(公告)号:US11575957B2
公开(公告)日:2023-02-07
申请号:US17322148
申请日:2021-05-17
发明人: Junsik Choi , Jungrae Kim , Jinyong Park , Hyunyong Choi , Dongwook Han , Jina Kwon , Hayeon Kil , Kyoungmin Kim , Youngjin Kim , Sungyong Park , Siyoung Park , Yongwoo Shin , Daesik Yoon , Eunjoo Cho , Jungyon Cho
IPC分类号: H04N21/422 , G06F3/14 , G06F3/16
摘要: A display device and a method capable of rotating a display based on a type of a user command are provided. The display device according to the disclosure receives a user command while first content is displayed on the display, the display being configured to operate in a first orientation while displaying the first content, maintains the display to operate in the first orientation when the received user command is a command to control a feature corresponding to the first content, determines, based on a type of a second content, to control the display to operate in the first orientation or a second orientation different from the first orientation when the received user command is a command to display the second content on the display, and controls the motor to rotate the display based on the determined first orientation or the second orientation.
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公开(公告)号:US11321040B2
公开(公告)日:2022-05-03
申请号:US16588078
申请日:2019-09-30
发明人: Seungyeon Jeong , Dongwook Han , Kyoungmin Kim , Daegyu Bae , Geunsam Yang , Sukun Yoon , Kangil Chung
IPC分类号: G06F3/14 , G06F3/16 , G11B27/34 , H04N21/41 , H04N21/431 , H04N21/435 , H04N21/4363
摘要: The present disclosure relates to a display device, a user terminal device, a method for controlling a display device, and a method for controlling a user terminal device. The disclosure relates to a method in which a display device outputs content that is being output via a user terminal device based on a content request event associated with a request for the display device to output information associated with content that is being output via the user terminal device.
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公开(公告)号:US12106795B2
公开(公告)日:2024-10-01
申请号:US17724006
申请日:2022-04-19
发明人: Myeongsik Ryu , Bokyeon Won , Kyoungmin Kim , Donggeon Kim , Sangwook Park , Inseok Baek
IPC分类号: G11C11/408
CPC分类号: G11C11/4085
摘要: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.
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公开(公告)号:US11735248B2
公开(公告)日:2023-08-22
申请号:US17685849
申请日:2022-03-03
发明人: Seokjae Lee , Bok-Yeon Won , Kyoungmin Kim , Donggeon Kim , Myeongsik Ryu , Sangwook Park , Inseok Baek
IPC分类号: G11C11/408 , H10B12/00
CPC分类号: G11C11/4085 , H10B12/50 , H10B12/315 , H10B12/34
摘要: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.
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公开(公告)号:US11726735B2
公开(公告)日:2023-08-15
申请号:US17698647
申请日:2022-03-18
发明人: Seungyeon Jeong , Dongwook Han , Kyoungmin Kim , Daegyu Bae , Geunsam Yang , Sukun Yoon , Kangil Chung
IPC分类号: G06F3/14 , G06F3/16 , G11B27/34 , H04N21/41 , H04N21/431 , H04N21/4363
CPC分类号: G06F3/1423 , G06F3/165 , G11B27/34
摘要: The present disclosure relates to a display device, a user terminal device, a method for controlling a display device, and a method for controlling a user terminal device. The disclosure relates to a method in which a display device outputs content that is being output via a user terminal device based on a content request event associated with a request for the display device to output information associated with content that is being output via the user terminal device.
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公开(公告)号:US20220406360A1
公开(公告)日:2022-12-22
申请号:US17685849
申请日:2022-03-03
发明人: Seokjae Lee , Bok-Yeon Won , Kyoungmin Kim , Donggeon Kim , Myeongsik Ryu , Sangwook Park , Inseok Baek
IPC分类号: G11C11/408 , H01L27/108
摘要: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.
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公开(公告)号:US20240363157A1
公开(公告)日:2024-10-31
申请号:US18538260
申请日:2023-12-13
发明人: Kyoungmin Kim , Inseok Baek , Donggeon Kim , Myeongsik Ryu , Sangwook Park , Sujin Park , Bokyeon Won , Jongmoon Yoon
IPC分类号: G11C11/4094 , G11C11/4091 , G11C11/4099
CPC分类号: G11C11/4094 , G11C11/4091 , G11C11/4099
摘要: A memory device includes first global bitlines adjacent to a first edge portion of a memory cell region, second global bitlines adjacent to a second edge portion of the memory cell region; dummy global bitlines in a central portion of the memory cell region, and a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines A first layer of the memory cell region is connected to a second layer of the sense amplifier region and is configured to apply a bias voltage to each of the dummy global bitlines.
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公开(公告)号:US11818881B2
公开(公告)日:2023-11-14
申请号:US17709971
申请日:2022-03-31
发明人: Kyoungmin Kim , Donggeon Kim , Myeongsik Ryu , Sangwook Park , Inseok Baek , Bokyeon Won
IPC分类号: G11C11/40 , H10B12/00 , H01L25/065 , G11C11/408 , H01L29/423 , H01L23/498
CPC分类号: H10B12/50 , G11C11/4085 , H01L25/0652 , H01L29/4238 , H01L23/49816 , H01L23/49833 , H01L2225/06513 , H01L2225/06541
摘要: A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.
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