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    Integrated circuit devices
    2.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US11437089B2

    公开(公告)日：2022-09-06

    申请号：US17245334

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

    IPC: G11C11/4091 ,  H01L27/108

    Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

    Memory device having sub wordline driver
    5.
    发明授权
    Memory device having sub wordline driver 有权

    公开(公告)号：US12106795B2

    公开(公告)日：2024-10-01

    申请号：US17724006

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeongsik Ryu ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Sangwook Park ,  Inseok Baek

    IPC: G11C11/408

    CPC classification number: G11C11/4085

    Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
    8.
    发明申请
    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME 有权

    公开(公告)号：US20220406360A1

    公开(公告)日：2022-12-22

    申请号：US17685849

    申请日：2022-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

    IPC: G11C11/408 ,  H01L27/108

    Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

    BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    9.
    发明申请
    BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250085858A1

    公开(公告)日：2025-03-13

    申请号：US18591238

    申请日：2024-02-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donggeon Kim ,  Myeongsik Ryu ,  Bokyeon Won ,  Seokjae Lee ,  Daehyeon Kwon ,  Kyoungmin Kim ,  Inseok Baek ,  Selyung Yoon

    IPC: G06F3/06

    Abstract: A bit-line sense amplifier includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer. The amplifying circuit is connected to a bit-line and a complementary bit-line, senses a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjusts a voltage of a sensing bit-line and a complementary sensing bit-line based on the voltage difference. The equalizer is connected to the sensing bit-line, and equalizes the bit-line and the complementary bit-line to a precharge voltage, based on an equalizing signal. The equalizer includes an equalizing transistor that has a source, a gate configured to receive the equalizing signal, and a drain. The source of the equalizing transistor is connected to a wiring structure through a direct contact, and the wiring structure is configured to receive the precharge voltage.

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