公开(公告)号：US20240096401A1

公开(公告)日：2024-03-21

申请号：US18199114

申请日：2023-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Young KIM ,  Sang-Yun KIM ,  Younghun SEO

IPC: G11C11/4091 ,  G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  H10B12/50

Abstract: A semiconductor memory device is provided which is capable of adaptively controlling bias and a method of operating the same. The semiconductor memory device includes: a memory cell area including a plurality of first transistors to which a first bias voltage is applied; and a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second bias voltage controlled differently from the first bias voltage is applied.

公开(公告)号：US20230064611A1

公开(公告)日：2023-03-02

申请号：US17748357

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoseok LEE ,  Sunyoung KIM ,  Younghun SEO

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/4094

Abstract: A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

公开(公告)号：US20240339153A1

公开(公告)日：2024-10-10

申请号：US18746974

申请日：2024-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok LEE ,  Sunyoung KIM ,  Younghun SEO

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

公开(公告)号：US20240064973A1

公开(公告)日：2024-02-22

申请号：US18106620

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juwon LIM ,  Younghun SEO ,  Sang-Yun KIM

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.

公开(公告)号：US20210241818A1

公开(公告)日：2021-08-05

申请号：US17002002

申请日：2020-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongil LEE ,  Younghun SEO

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/56

Abstract: A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

公开(公告)号：US20210027830A1

公开(公告)日：2021-01-28

申请号：US16812850

申请日：2020-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyun KIM ,  Younghun SEO ,  Hyejung KWON ,  Myungkyu LEE ,  Sunghye CHO

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.