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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210027830A1

    公开(公告)日：2021-01-28

    申请号：US16812850

    申请日：2020-03-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyun KIM ,  Younghun SEO ,  Hyejung KWON ,  Myungkyu LEE ,  Sunghye CHO

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

    CALIBRATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    3.
    发明公开
    CALIBRATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230186958A1

    公开(公告)日：2023-06-15

    申请号：US17903578

    申请日：2022-09-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyeok BAEK ,  Daehyun KWON ,  Hyejung KWON ,  Donggun AN ,  Daewoong LEE

    IPC: G11C7/10

    CPC classification number: G11C7/1048 ,  G11C2207/2254

    Abstract: A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.

    APPARATUS, MEMORY DEVICE AND METHOD FOR STORING PARAMETER CODES FOR ASYMMETRIC ON-DIE- TERMINATION
    4.
    发明申请
    APPARATUS, MEMORY DEVICE AND METHOD FOR STORING PARAMETER CODES FOR ASYMMETRIC ON-DIE- TERMINATION 有权

    公开(公告)号：US20220321125A1

    公开(公告)日：2022-10-06

    申请号：US17591093

    申请日：2022-02-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daehyun KWON ,  Hyejung KWON ,  Hyeran KIM ,  Chisung OH

    IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17772 ,  H03K19/17736

    Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

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