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    Programmable logic device
    4.
    发明授权
    Programmable logic device 有权

    公开(公告)号：US09680476B2

    公开(公告)日：2017-06-13

    申请号：US15163817

    申请日：2016-05-25

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yoshiyuki Kurokawa ,  Takayuki Ikeda

    IPC分类号： H03K19/177 ,  H03K19/0944 ,  H03K19/173

    CPC分类号： H03K19/1776 ,  H03K19/0944 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17772 ,  H03K19/17776

    摘要： A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09570445B2

    公开(公告)日：2017-02-14

    申请号：US14339948

    申请日：2014-07-24

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Kazuaki Ohshima

    IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H03K19/00 ,  H03K19/177

    CPC分类号： H01L27/105 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/108 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/1776 ,  H03K19/17772

    摘要： A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.

    摘要翻译： 提供具有新颖结构的半导体器件。 半导体器件包括第一p型晶体管，第二n型晶体管，第三晶体管和第四晶体管。 第三晶体管的源极和漏极之一连接到提供第一电位的布线，另一个连接到第一晶体管的源极和漏极之一。 第二晶体管的源极和漏极之一连接到第一晶体管的源极和漏极中的另一个，另一个连接到第四晶体管的源极和漏极之一。 第四晶体管的源极和漏极中的另一个连接到提供低于第一电位的第二电位的布线。 在第三晶体管和第四晶体管的沟道形成区域中使用氧化物半导体材料。

    Method of driving semiconductor device
    6.
    发明授权
    Method of driving semiconductor device 有权

    公开(公告)号：US09503087B2

    公开(公告)日：2016-11-22

    申请号：US14680203

    申请日：2015-04-07

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Yasuhiko Takemura

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/094 ,  H03K19/00 ,  H03K19/177

    CPC分类号： H03K19/003 ,  H03K19/0016 ,  H03K19/094 ,  H03K19/1776 ,  H03K19/17772

    摘要： A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.

    Power management system for integrated circuits
    7.
    发明授权
    Power management system for integrated circuits 有权
    集成电路电源管理系统

    公开(公告)号：US09419624B2

    公开(公告)日：2016-08-16

    申请号：US14539697

    申请日：2014-11-12

    申请人： Xilinx, Inc.

    发明人： Austin H. Lesea

    IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/0175

    CPC分类号： H03K19/17772 ,  H03K19/00384 ,  H03K19/017509 ,  H03K19/17784

    摘要： An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.

    摘要翻译： 一种装置包括多个可编程硬件资源和设置在IC芯片上的模数转换器（ADC）。 ADC被配置为量化IC芯片的一个或多个模拟参数的值。 该装置还包括配置控制电路，配置为响应于一组配置数据对可编程硬件资源进行编程。 可编程硬件资源被编程为实现由配置数据指定的一组电路，并将ADC连接到IC芯片的相应节点，以对模拟参数进行采样。 该装置还包括耦合到ADC并被配置为基于来自ADC的一个或多个模拟参数的量化值产生控制信号的接口电路。 接口电路将控制信号输出到耦合到IC芯片的电源端子的电源。

    Programmable logic circuit
    8.
    发明授权
    Programmable logic circuit 有权
    可编程逻辑电路

    公开(公告)号：US09397664B2

    公开(公告)日：2016-07-19

    申请号：US14282288

    申请日：2014-05-20

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yoshiya Takewaki

    IPC分类号： H03K19/0175 ,  H03K19/0948 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/0948 ,  H03K19/1776 ,  H03K19/17772

    摘要： A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

    摘要翻译： 提供一种逻辑电路，即使在未提供电源电位时也能够保持逻辑电路的开关状态，在供电之后逻辑块的启动时间短，可以以低功耗工作，并且可以 容易地在NAND电路和NOR电路之间切换。 在NAND电路和NOR电路之间的切换是通过包括氧化物半导体的晶体管切换节点处的电荷保持状态来实现的。 通过使用作为晶体管的宽带隙半导体的氧化物半导体材料，可以充分降低晶体管的截止电流; 因此，在节点处保持的电荷状态可以是非易失性的。

    Programmable logic device
    9.
    发明授权
    Programmable logic device 有权
    可编程逻辑器件

    公开(公告)号：US09165942B2

    公开(公告)日：2015-10-20

    申请号：US13903165

    申请日：2013-05-28

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Tatsuji Nishijima

    IPC分类号： H03K19/177 ,  H01L25/00 ,  H01L27/118

    CPC分类号： H01L27/11803 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17772

    摘要： An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.

    摘要翻译： 本发明的目的是提供一种可编程逻辑器件，其在供电停止，高度集成并且以低功率运行后具有短的启动时间。 在包括输入/​​输出块，包括逻辑元件的多个逻辑块和连接多个逻辑块的布线的可编程逻辑器件中，逻辑元件具有用于保存配置数据和查找表的配置存储器 包括选择电路。 配置存储器包括多个存储元件，每个存储元件包括沟道区域在氧化物半导体膜中的晶体管和设置在晶体管和选择电路之间的运算电路。 配置数据根据输入信号由选择电路选择性地改变和输出。

    Logic circuit
    10.
    发明授权
    Logic circuit 有权
    逻辑电路

    公开(公告)号：US08779799B2

    公开(公告)日：2014-07-15

    申请号：US13467500

    申请日：2012-05-09

    申请人： Yoshiya Takewaki

    发明人： Yoshiya Takewaki

    IPC分类号： H03K19/20 ,  G11C11/34

    CPC分类号： H03K19/017581 ,  H03K19/0948 ,  H03K19/1776 ,  H03K19/17772

    摘要： A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

    摘要翻译： 提供一种逻辑电路，即使在未提供电源电位时也能够保持逻辑电路的开关状态，在供电之后逻辑块的启动时间短，可以以低功耗工作，并且可以 容易地在NAND电路和NOR电路之间切换。 在NAND电路和NOR电路之间的切换是通过包括氧化物半导体的晶体管切换节点处的电荷保持状态来实现的。 通过使用作为晶体管的宽带隙半导体的氧化物半导体材料，可以充分降低晶体管的截止电流; 因此，在节点处保持的电荷状态可以是非易失性的。