公开(公告)号：US20190004945A1

公开(公告)日：2019-01-03

申请号：US15640533

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Kermin Fleming ,  Kent D. Glossop ,  Simon C. Steely, JR. ,  Samantika S. Sury

IPC: G06F12/0802 ,  G06F17/50 ,  H03K19/177

CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F15/7867 ,  G06F15/8015 ,  G06F15/825 ,  G06F17/505 ,  G11C7/1012 ,  G11C8/12 ,  G11C2207/2245 ,  H03K19/17736 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an atomic operation when an incoming operand set arrives at the plurality of processing elements.

公开(公告)号：US20180113757A1

公开(公告)日：2018-04-26

申请号：US15737549

申请日：2015-06-22

Applicant: Hitachi, Ltd.

Inventor： Teruaki SAKATA ,  Tsutomu YAMADA

IPC: G06F11/08 ,  H03K19/177 ,  G01R31/3185

CPC classification number: G06F11/085 ,  B61L5/18 ,  G01R31/318519 ,  H03K19/173 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17776

Abstract: An object of the invention is to provide a field programmable gate array which is able to prevent an inappropriate value from being output to the outside of an FPGA even when an SRAM-based programmable logic portion is out of order and to secure safety of a system. The field programmable gate array of the invention includes a hard macro CPU in which a circuit structure is fixed, a programmable logic in which a circuit structure is changeable, a diagnosis circuit which diagnoses an abnormality of the programmable logic, and a fail-safe interface circuit which is able to control an external output from the programmable logic to a safe side, and the hard macro CPU outputs a fail-safe signal which is an output of a safe side to the fail-sate interface circuit when an error is detected by the diagnosis circuit.

公开(公告)号：US20180012637A1

公开(公告)日：2018-01-11

申请号：US15713281

申请日：2017-09-22

Applicant: Hare Krishna VERMA

Inventor： Hare Krishna VERMA

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/10 ,  G11C5/06 ,  H03K19/17756 ,  H03K19/17776

Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.

公开(公告)号：US09762246B2

公开(公告)日：2017-09-12

申请号：US13469143

申请日：2012-05-11

Applicant: Masashi Fujita ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidetomo Kobayashi

Inventor： Masashi Fujita ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidetomo Kobayashi

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17772 ,  H03K19/17776

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20160315619A1

公开(公告)日：2016-10-27

申请号：US14761410

申请日：2014-12-11

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Ping FAN ,  Jia GENG ,  Yuanpeng WANG

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/173

CPC classification number: H03K19/17728 ,  H03K19/0008 ,  H03K19/1732 ,  H03K19/1737 ,  H03K19/17776

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract translation: 多模支持和可配置的六输入查找表（LUT）的结构以及现场可编程门阵列（FPGA）装置。 六输入LUT具有六个信号输入端和两个信号输出端。 六输入LUT包括：第一五输入LUT，第二五输入LUT，第一多路复用器和第二多路复用器。 第一五输入LUT根据六输入LUT的五个信号输入端输入的五个数据信号输出第一输出信号，其中第一输出信号由六输入LUT的第一信号输出端输出; 第二五输入LUT根据由六输入LUT的五个信号输入端输入的五个数据信号输出第二输出信号; 并且所述第一多路复用器根据设定的配置模式输出控制信号，以控制所述第二多路复用器输出所述第一输出信号或所述第二输出信号。

公开(公告)号：US20160307612A1

公开(公告)日：2016-10-20

申请号：US15197356

申请日：2016-06-29

Applicant: ALTERA CORPORATION

Inventor： Jun Pin Tan ,  Kiun Kiet Jong ,  Lai Pheng Tan

IPC: G11C8/04 ,  G11C7/00

CPC classification number: G11C8/04 ,  G06F9/4403 ,  G11C7/00 ,  G11C7/1039 ,  H03K19/1776 ,  H03K19/17776

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract translation: 本文提供了用于实现可编程集成电路器件的系统和方法，其通过显着减少配置时间来实现高速FPGA引导。 通过启用高速FPGA启动，可编程集成电路器件将能够适应需要比常规可编程集成电路器件能够容纳的更快启动时间的应用。 为了实现高速引导，为数据线的每个数据线段实现专用地址寄存器，这又大大减少了配置随机存取存储器（CRAM）写入时间（例如，至少两倍） ）。

公开(公告)号：US09437260B2

公开(公告)日：2016-09-06

申请号：US14395555

申请日：2013-04-24

Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

Inventor： Guillaume Prenat ,  Olivier Goncalves

IPC: G11C7/10 ,  H03K19/003 ,  H03K19/177

CPC classification number: G11C7/1045 ,  H03K19/0033 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

Abstract: The invention relates to a reprogrammable logic device comprising a plurality of elementary patches, each patch comprising: at least one logic block configurable by one or more volatile memory cells storing configuration data; and a memory comprising: a plurality of non-volatile memory cells storing refresh data, each non-volatile memory cell comprising first and second resistance-switching elements, each being programmable so as to have one of a first and of a second resistance value representative of the refresh data; and a read-write circuit adapted for periodically refreshing the configuration data on the basis of the refresh data.

Abstract translation: 本发明涉及一种包括多个基本补丁的可再编程逻辑器件，每个补丁包括：由一个或多个存储配置数据的易失性存储单元配置的至少一个逻辑块; 以及存储器，包括：存储刷新数据的多个非易失性存储单元，每个非易失性存储单元包括第一和第二电阻切换元件，每个非易失性存储单元可编程为具有第一和第二电阻值代表中的一个 的刷新数据; 以及适于基于刷新数据周期性地刷新配置数据的读写电路。

公开(公告)号：US20160154602A1

公开(公告)日：2016-06-02

申请号：US14941430

申请日：2015-11-13

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yosuke Obayashi

IPC: G06F3/06

CPC classification number: H03K19/17756 ,  H03K19/17776

Abstract: An information processing apparatus includes a first storage unit to store a plurality of pieces of circuit configuration information corresponding to the respective plurality of partial reconfiguration portions, preloads a piece of circuit configuration information corresponding to one of the partial reconfiguration portions into a second storage unit having an access speed higher than an access speed of the first storage unit, and based on an operation status of the one partial reconfiguration portion, configures a logic circuit in the one partial reconfiguration portion, using the piece of circuit configuration information corresponding to the one partial reconfiguration portion that has been preloaded into the second storage unit, or configures a logic circuit in a partial reconfiguration portion different from the one partial reconfiguration portion, using a piece of circuit configuration information corresponding to the different partial reconfiguration portion that has been stored in the first storage unit.

Abstract translation: 信息处理设备包括：第一存储单元，用于存储与多个部分重新配置部分相对应的多条电路配置信息，将与该部分重新配置部分之一相对应的一条电路配置信息预加载到具有 访问速度高于第一存储单元的访问速度，并且基于一个部分重新配置部分的操作状态，使用与一个部分重新配置部分相对应的电路配置信息来配置一个部分重新配置部分中的逻辑电路 重新配置部分，其被预加载到第二存储单元中，或者使用与已经存储的不同的部分重新配置部分相对应的电路配置信息来配置不同于一个部分重新配置部分的部分重新配置部分中的逻辑电路 在第一个存储单元中。

公开(公告)号：US09257988B2

公开(公告)日：2016-02-09

申请号：US14478856

申请日：2014-09-05

Applicant: Board of Supervisors of Louisiana State University and Agricultural and Mechanical College

Inventor： Ramachandran Vaidyanathan ,  Matthew Jordan

IPC: G06F12/10 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17776 ,  H03K19/1732 ,  H03K19/17744 ,  H03K19/17752 ,  H03K19/17756

Abstract: The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x

Abstract translation: 本发明涉及将少量输入位有效地扩展到大量输出位的硬件解码器，同时在选择输出实例方面提供相当大的灵活性。 本发明的一个主要应用领域是引脚限制环境，例如与动态重新配置一起使用的现场可编程门阵列（FPGA）。 本发明包括映射单元，其是可能与可重新配置的存储器件组合的电路。 电路具有作为输入的z位源字，其在每个位位置具有值，并且其输出n位输出字，其中n> z，其中n位输出字的每个位位置的值基于 通过选择器地址选择所述预选硬连线位位置的x位字中的预选硬连线位之一的值。 本发明可以包括基于输入到第二存储器设备的x位源地址输出z位源字的第二可重构存储器件，其中x

公开(公告)号：US08664974B2

公开(公告)日：2014-03-04

申请号：US13011840

申请日：2011-01-21

Applicant: Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

Inventor： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC: H03K19/173 ,  H01L25/00 ,  G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Abstract translation: 具有几个可重新配置电路的可重构集成电路（“IC”），每个可配置电路在几个配置周期中具有多种配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。