公开(公告)号：US20240337684A1

公开(公告)日：2024-10-10

申请号：US18296598

申请日：2023-04-06

Applicant: Hamilton Sundstrand Space Systems International, Inc.

Inventor： Joshua Todd ,  Gabriel Fletcher

IPC: G01R31/28 ,  G01T1/02 ,  H03K19/003

CPC classification number: G01R31/2872 ,  G01T1/026 ,  H03K19/0033

Abstract: A system for detecting radiation events, having: a test memory with memory blocks; a controller having controller memory; an integrated circuit (IC) array having IC chains, wherein each of the IC chains has a plurality of IC elements that is response to and generates a voltage when exposed to a radiation event; a dosimeter configured to record an accumulated amount of radiation exposure to the system, wherein the controller is configured to perform steps of: initializing the test memory, the IC array and the dosimeter; monitoring for an unexpected signal from an IC chain and for unexpected data in a memory block of the test memory; and identifying the radiation event upon one or more of receiving the unexpected signal and identifying unexpected data in a memory block of the test memory.

公开(公告)号：US20170338824A1

公开(公告)日：2017-11-23

申请号：US15627157

申请日：2017-06-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas

IPC: H03K19/177 ,  H03K19/003 ,  H01L23/00

CPC classification number: H03K19/17768 ,  G06F21/75 ,  G06F21/87 ,  G09C1/00 ,  H01L23/576 ,  H03K19/0033 ,  H03K19/17704 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.

公开(公告)号：US09513903B2

公开(公告)日：2016-12-06

申请号：US14054643

申请日：2013-10-15

Applicant: Industrial Technology Research Institute

Inventor： Yung-Chang Chang ,  Hsing-Chuang Liu ,  Chih-Jen Yang

IPC: G06F11/16 ,  G06F9/30 ,  G06F11/18 ,  H03K19/003 ,  G06F11/14

CPC classification number: G06F9/3001 ,  G06F11/1497 ,  G06F11/1608 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/188 ,  H03K19/0033

Abstract: A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.

Abstract translation: 提供了包括计算单元和输出合成器的容错系统。 计算单元接收第一环境参数和输入数据，其中所述计算单元还包括第一和第二计算电路。 第一计算电路被配置为响应于第一环境参数对输入数据进行计算以产生第一计算结果。 第二计算电路与第一计算电路不同，并且被配置为响应于第一环境参数对输入数据进行计算以产生第二计算结果。 输出合成器根据控制信号从第一和第二计算结果中选择第一组和第二组，并且顺序地合成第一组位和第二组位，以产生经调整的计算结果。

公开(公告)号：US20160028397A1

公开(公告)日：2016-01-28

申请号：US14808348

申请日：2015-07-24

Applicant: Lawrence T. Clark

Inventor： Lawrence T. Clark

IPC: H03K19/003 ,  H03K3/2893 ,  H03K19/007

CPC classification number: H03K19/0033 ,  H03K19/0075

Abstract: This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.

Abstract translation: 本公开一般涉及辐射硬化的数字电路。 在一个实施例中，辐射硬化的数字电路包括延迟网络和第一Muller C元件。 延迟网络被配置为从全局时钟信号产生第一延迟时钟信号，使得第一延迟时钟信号相对于全局时钟信号被延迟。 第一Muller C元件被配置为产生第一时钟输入信号，并且响应于第一延迟时钟信号和全局时钟信号将第一时钟输入信号设置为一组时钟状态中的一个，每个时钟信号分别以 一组时钟状态，并被配置为保持第一个时钟输入信号。 因此，防止辐射打击在第一时钟输入信号中引起软错误。

公开(公告)号：US09000529B1

公开(公告)日：2015-04-07

申请号：US13666159

申请日：2012-11-01

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  James Karp ,  Michael J. Hart ,  Ramakrishna K. Tanikella

IPC: H01L21/70 ,  H01L29/06

CPC classification number: H01L29/0646 ,  H01L27/0207 ,  H03K19/0033

Abstract: A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.

Abstract translation: 电路包括实现在p型衬底内的互补金属氧化物半导体（CMOS）存储元件和在p型衬底内实现的与存储元件无关的n阱。 n阱和存储元件分开最小距离，其中p型衬底不包括n阱。

公开(公告)号：US20140157223A1

公开(公告)日：2014-06-05

申请号：US14060162

申请日：2013-10-22

Applicant: Klas Olof Lilja

Inventor： Klas Olof Lilja

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

Abstract: In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

Abstract translation: 在各种实施例中，公开了集成电路布局。 在一个实施例中，集成电路布局包括来自第一逻辑单元的第一接触区域和来自第二逻辑单元的第二接触区域。 第二接触区域包括相对于第一接触区域的非零非相反效应。 第一接触区域和第二接触区域包括第一距离。 当第一距离低于预定阈值时，第一逻辑单元和第二逻辑单元沿着电路的第一R线布置，并且第三接触区域包括相对于第一接触区域和第二接触区域的相反作用 被放置在第一接触区域和第二接触区域之间。

公开(公告)号：US20140019921A1

公开(公告)日：2014-01-16

申请号：US14026648

申请日：2013-09-13

Applicant: Robust Chip, Inc.

Inventor： Klas Olof Lilja

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Abstract translation: 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于调制解调器技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。

公开(公告)号：US20130227499A1

公开(公告)日：2013-08-29

申请号：US13463706

申请日：2012-05-03

Applicant: Klas Olof Lilja

Inventor： Klas Olof Lilja

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Abstract translation: 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于调制解调器技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。

公开(公告)号：US08421503B2

公开(公告)日：2013-04-16

申请号：US12715815

申请日：2010-03-02

Applicant: Taiki Uemura ,  Yoshiharu Tosaka

Inventor： Taiki Uemura ,  Yoshiharu Tosaka

IPC: H03K19/094 ,  H03K3/356

CPC classification number: H03K3/356156 ,  G01R31/31816 ,  H03K3/0375 ,  H03K19/0033

Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.

Abstract translation: 锁存电路包括接收外部输入信号的输入部分; 多个CMOS反相器电路，分为第一组，其包括第一CMOS反相器电路和输出相对于输入信号的反相数据的第二CMOS反相器电路;以及第二组，其包括第三CMOS反相器电路和第四CMOS反相器 电路输出与输入信号相同的数据; 以及反馈路径，通过所述反馈路径，所述输入信号经由所述多个CMOS反相器电路被反馈到所述输入部，其中属于所述第一CMOS反相器电路和所述第二CMOS反相器电路之一的第二极性漏极被布置在第一 属于第一CMOS反相器电路的漏极漏极和属于第二CMOS反相器电路的第一极性漏极。

公开(公告)号：US08390327B1

公开(公告)日：2013-03-05

申请号：US13214040

申请日：2011-08-19

Applicant: Charles Parkhurst ,  Mark Hamlyn

Inventor： Charles Parkhurst ,  Mark Hamlyn

IPC: H03K19/0175

CPC classification number: H03K19/0033

Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.

Abstract translation: 公开了用于辐射耐受电平转换的系统和方法。 在一些实施例中，集成电路可以包括多个电平移位器，其中配置的多个电平移位器中的每一个在第一电压域中接收相同的逻辑电平，并且在第二电压域中输出候选逻辑电平，并且至少在 候选逻辑电平之一与候选逻辑电平中的另一个不同。 集成电路还可以包括耦合到多个电平移位器的投票电路，其中投票电路被配置为评估候选逻辑电平并且至少部分地基于评估来输出所选择的逻辑电平。