公开(公告)号：US09083341B2

公开(公告)日：2015-07-14

申请号：US13692800

申请日：2012-12-03

Applicant: Robust Chip Inc.

Inventor： Klas Olof Lilja

IPC: G06F17/50 ,  H03K19/003 ,  H03K19/21 ,  H03K19/20 ,  H03K21/10

CPC classification number: H03K19/215 ,  G06F17/50 ,  G06F17/5072 ,  H03K19/00338 ,  H03K19/20 ,  H03K21/10

Abstract: A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.

Abstract translation: 公开了一种用于从原始逻辑集成电路门创建逻辑集成电路单元的方法。 该方法包括将原始逻辑集成电路单元与作为输入的原始逻辑集成电路单元的输入的补码相结合的第二电路组合，并提供原始逻辑集成电路单元的输出的输出补码。 该方法还包括连接组合的逻辑集成电路单元，其中组合集成电路单元的输出为其它组合电路单元提供输入，使得当来自第一组合逻辑集成电路单元的原始逻辑集成电路的输出为 连接到第二组合逻辑集成电路单元的输入，则第一组合逻辑集成电路单元中的第二电路的输出总是也连接到第二组合逻辑集成电路单元，其作为来自 原有的逻辑集成电路单元。

公开(公告)号：US20130162293A1

公开(公告)日：2013-06-27

申请号：US13692800

申请日：2012-12-03

Applicant: ROBUST CHIP INC.

Inventor： Klas Olof Lilja

IPC: H03K19/21 ,  G06F17/50 ,  H03K19/20

CPC classification number: H03K19/215 ,  G06F17/50 ,  G06F17/5072 ,  H03K19/00338 ,  H03K19/20 ,  H03K21/10

Abstract: A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.

Abstract translation: 公开了一种用于从原始逻辑集成电路门创建逻辑集成电路单元的方法。 该方法包括将原始逻辑集成电路单元与作为输入的原始逻辑集成电路单元的输入的补码相结合的第二电路组合，并提供原始逻辑集成电路单元的输出的输出补码。 该方法还包括连接组合的逻辑集成电路单元，其中组合集成电路单元的输出为其它组合电路单元提供输入，使得当来自第一组合逻辑集成电路单元的原始逻辑集成电路的输出为 连接到第二组合逻辑集成电路单元的输入，则第一组合逻辑集成电路单元中的第二电路的输出总是也连接到第二组合逻辑集成电路单元，其作为来自 原有的逻辑集成电路单元。

公开(公告)号：US20140019921A1

公开(公告)日：2014-01-16

申请号：US14026648

申请日：2013-09-13

Applicant: Robust Chip, Inc.

Inventor： Klas Olof Lilja

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Abstract translation: 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于调制解调器技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。