Invention Application
- Patent Title: Soft Error Hard Electronics Layout Arrangement and Logic Cells
- Patent Title (中): 软错误硬电子布局布置和逻辑单元
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Application No.: US13692800Application Date: 2012-12-03
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Publication No.: US20130162293A1Publication Date: 2013-06-27
- Inventor: Klas Olof Lilja
- Applicant: ROBUST CHIP INC.
- Applicant Address: US CA Pleasanton
- Assignee: ROBUST CHIP INC.
- Current Assignee: ROBUST CHIP INC.
- Current Assignee Address: US CA Pleasanton
- Main IPC: H03K19/21
- IPC: H03K19/21 ; G06F17/50 ; H03K19/20

Abstract:
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.
Public/Granted literature
- US09083341B2 Soft error resilient circuit design method and logic cells Public/Granted day:2015-07-14
Information query
IPC分类: