Fast recovery for dual core lock step

    公开(公告)号:US11928475B2

    公开(公告)日:2024-03-12

    申请号:US17519588

    申请日:2021-11-05

    申请人: Ceremorphic, Inc.

    发明人: Heonchul Park

    IPC分类号: G06F9/30 G06F9/38 G06F11/16

    摘要: An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.

    LOOSELY-COUPLED LOCK-STEP CHAINING
    8.
    发明申请

    公开(公告)号:US20180349214A1

    公开(公告)日:2018-12-06

    申请号:US15610139

    申请日:2017-05-31

    IPC分类号: G06F9/54 G06F11/16

    摘要: A system and method enables loosely-coupled lock-step computing including sensors that detect or measure a physical property and server groups. Each server group is serially linked to another server group and includes server instances operating in virtual synchrony. Virtual synchrony middleware receives outputs from multiple server instances and renders a single reply based on the outputs from the multiple server instances. The virtual synchrony middleware replicates and orders incoming requests to the server groups to ensure each of the server instances of that server group receives the same incoming requests in the same order.