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    Page retirement techniques for multi-page DRAM faults
    1.
    发明授权
    Page retirement techniques for multi-page DRAM faults 有权

    公开(公告)号：US12216539B2

    公开(公告)日：2025-02-04

    申请号：US17977001

    申请日：2022-10-31

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan ,  Majed Valad Beigi

    IPC: G06F11/30 ,  G06F11/07 ,  G06F11/10 ,  G06F12/1027

    Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).

    Using Multiple Functional Blocks for Training Neural Networks
    4.
    发明申请
    Using Multiple Functional Blocks for Training Neural Networks 审中-公开

    公开(公告)号：US20200151572A1

    公开(公告)日：2020-05-14

    申请号：US16191359

    申请日：2018-11-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi

    IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04

    Abstract: A system is described that performs training operations for a neural network, the system including an analog circuit element functional block with an array of analog circuit elements, and a controller. The controller monitors error values computed using an output from each of one or more initial iterations of a neural network training operation, the one or more initial iterations being performed using neural network data acquired from the memory. When one or more error values are less than a threshold, the controller uses the neural network data from the memory to configure the analog circuit element functional block to perform remaining iterations of the neural network training operation. The controller then causes the analog circuit element functional block to perform the remaining iterations.

    RESILIENT VERTICAL STACKED CHIP NETWORK
    5.
    发明申请
    RESILIENT VERTICAL STACKED CHIP NETWORK 审中-公开

    公开(公告)号：US20180300265A1

    公开(公告)日：2018-10-18

    申请号：US15490036

    申请日：2017-04-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Roberts ,  Sudhanva Gurumurthi

    IPC: G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G11C5/06

    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked memory are disclosed. A computing system includes a host processor die and multiple vertically stacked memory dies. The host processor die generates memory access requests for the data stored in the multiple memory array banks in the memory dies. At least one memory die uses an on-die network switch with a programmable routing table for routing packets corresponding to the generated memory requests. Routes use both vertical hops and horizontal hops to reach the target memory array bank and to avoid any congested or failed resources along the route. The vertically stacked memory dies use through silicon via interconnects and at least one via does not traverse through all of the memory dies. Accordingly, the host processor die does not have a direct connection to one or more of the multiple memory dies.

    INFRASTRUCTURE TO SUPPORT ACCELERATOR COMPUTATION MODELS FOR ACTIVE STORAGE
    6.
    发明申请
    INFRASTRUCTURE TO SUPPORT ACCELERATOR COMPUTATION MODELS FOR ACTIVE STORAGE 审中-公开
    支持主动存储的加速器计算模型的基础设施

    公开(公告)号：US20160335064A1

    公开(公告)日：2016-11-17

    申请号：US14709915

    申请日：2015-05-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shuai Che ,  Sudhanva Gurumurthi ,  Michael W. Boyer

    IPC: G06F9/45 ,  G06F9/44

    CPC classification number: G06F8/447 ,  G06F8/4434

    Abstract: A method, a system, and a non-transitory computer readable medium for generating application code to be executed on an active storage device are presented. The parts of an application that can be executed on the active storage device are determined. The parts of the application that will not be executed on the active storage device are converted into code to be executed on a host device. The parts of the application that will be executed on the active storage device are converted into code of an instruction set architecture of a processor in the active storage device.

    Abstract translation: 呈现用于生成要在活动存储设备上执行的应用代码的方法，系统和非暂时性计算机可读介质。 可以在活动存储设备上执行的应用程序的部分被确定。 将不会在活动存储设备上执行的应用程序的部分被转换为要在主机设备上执行的代码。 将在活动存储设备上执行的应用的部分被转换为主动存储设备中的处理器的指令集架构的代码。

    Host-level error detection and fault correction
    7.
    发明授权
    Host-level error detection and fault correction 有权

    公开(公告)号：US12013752B2

    公开(公告)日：2024-06-18

    申请号：US17841864

    申请日：2022-06-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1004 ,  G06F11/0772 ,  G06F11/102 ,  G06F11/1068

    Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.

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