公开(公告)号：US11755298B2

公开(公告)日：2023-09-12

申请号：US17516393

申请日：2021-11-01

Applicant: APEX.AI, INC.

Inventor： Misha Shalem

IPC: G06F8/41 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F8/4434 ,  G06F8/42 ,  G06F8/433 ,  G06F12/02 ,  G06F12/06 ,  G06F2212/1008

Abstract: Deterministic memory allocation for real-time applications. In an embodiment, bitcode is scanned to detect calls by a memory allocation function to a dummy function. Each call uses parameters comprising an identifier of a memory pool and a size of a data type to be stored in the memory pool. For each detected call, an allocation record, comprising the parameters, is generated. Then, a header file is generated based on the allocation records. The header file may comprise a definition of bucket(s) and a definition of memory pools. Each definition of a memory pool may identify at least one bucket.

公开(公告)号：US20190187964A1

公开(公告)日：2019-06-20

申请号：US15848476

申请日：2017-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark U. Wyse ,  Bradford Michael Beckmann ,  John Kalamatianos ,  Anthony Thomas Gutierrez

IPC: G06F8/41

CPC classification number: G06F8/4434 ,  G06F8/433

Abstract: Systems, apparatuses, and methods for converting computer program source code from a first high level language to a functionally equivalent executable program code. Source code in a first high level language is analyzed by a code compilation tool. In response to identifying a potential bank conflict in a multi-bank register file, operands of one or more instructions are remapped such that they map to different physical banks of the multi-bank register file. Identifying a potential bank conflict comprises one or more of identifying an intra-instruction bank conflict, an inter-instruction bank conflict, and identifying a multi-word operand with a potential bank conflict.

公开(公告)号：US20180373515A1

公开(公告)日：2018-12-27

申请号：US15632286

申请日：2017-06-23

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC.

Inventor： MORGAN ASHER BROWN ,  DAVID CHARLES WRIGHTON ,  MEI-CHIN TSAI ,  SHAH MOHAMMAD FAIZUR RAHMAN ,  YI ZHANG ,  IAN M. BEARMAN ,  ERDEMBILEGT JANCHIVDORJ ,  DAVID ADAM HARTGLASS ,  DAVID MITFORD GILLIES

IPC: G06F9/45

CPC classification number: G06F8/4441 ,  G06F8/433 ,  G06F8/4434 ,  G06F8/4443 ,  G06F8/447 ,  G06F9/4552

Abstract: A mechanism for generating optimized native code for a program having dynamic behavior uses a static analysis of the program to predict the likelihood that different elements of the program are likely to be used when the program executes. The static analysis is performed prior to execution of the program and marks certain elements of the program with confidence indicators that classify the elements with either a high level of confidence or a low level of confidence. The confidence indicators are then used by an ahead-of-time native compiler to generate native code and to optimize the code for faster execution and/or a smaller-sized native code.

公开(公告)号：US20180167480A1

公开(公告)日：2018-06-14

申请号：US15375782

申请日：2016-12-12

Applicant: SAP SE

Inventor： Shashank Mohan Jain

IPC: H04L29/08 ,  G06F9/45 ,  G06F9/44

CPC classification number: H04L67/2828 ,  G06F8/30 ,  G06F8/41 ,  G06F8/433 ,  G06F8/4434 ,  G06F9/45504 ,  H04L67/02 ,  H04L67/10 ,  H04L67/42

Abstract: A system and method of reducing network bandwidth for application development are provided. The method comprises receiving from a developer platform (i) core application software and (ii) dependency software associated with the core application software. The compiled dependency software is transmitted to a first server associated with cloud storage. The compiled core application software is transmitted to a second server associated with the cloud storage. An application based on the compiled core application software and the compiled dependency software may be executed.

公开(公告)号：US20180107465A1

公开(公告)日：2018-04-19

申请号：US15297606

申请日：2016-10-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Michal Silbermintz ,  John Russo

IPC: G06F9/45

CPC classification number: G06F8/4434 ,  G06F8/443 ,  G06F8/447

Abstract: A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. The builder module to build executable applications for the target processor based on a set of instructions. The call graph generator to create a first call graph that indicates a stack usage for each call path of the executable applications. If a first executable application built by the builder module includes a call path that exceeds a stack size constraint of the target processor, the builder module to optimize only functions within the call path that exceeds the stack size constraint in response to the request from the evaluation monitor, and to build a second executable application based on the set of instructions. The second executable application is optimized for stack memory usage of the target processor.

公开(公告)号：US20180095736A1

公开(公告)日：2018-04-05

申请号：US15850668

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Yaoqing Gao ,  William G. O'Farrell ,  Denis Palmeiro

IPC: G06F9/45 ,  G06F9/52 ,  G06F9/46

CPC classification number: G06F8/434 ,  G06F8/41 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/4441 ,  G06F8/458 ,  G06F9/467 ,  G06F9/52

Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.

公开(公告)号：US20180088913A1

公开(公告)日：2018-03-29

申请号：US15710561

申请日：2017-09-20

Applicant: Airbus Operations (S.A.S.)

Inventor： Dominique PORTES ,  Victor JEGU

IPC: G06F9/44 ,  G06F9/30

CPC classification number: G06F8/35 ,  G06F8/10 ,  G06F8/37 ,  G06F8/4434 ,  G06F8/73 ,  G06F9/30007 ,  G06F9/30145 ,  G06F9/45508

Abstract: System and method to generate automatically a compact application code suitable for taking advantage of the intrinsic power of processors. The system can generate the application code executable by a processor from a formal specification associated with an application, the formal specification including operators, and the system including an analyzer to code each operator of the formal specification by a corresponding operation code followed by a minimum number of input code(s) and output code identifying input and output parameters associated with the operator, thus automatically generating a compact application code suitable for being stored in a memory associated with the processor and for being executed by an interpreter of the processor.

公开(公告)号：US09870204B2

公开(公告)日：2018-01-16

申请号：US14675696

申请日：2015-03-31

Applicant: CAVIUM, INC.

Inventor： Ajeer Salil Pudiyapura ,  Kishore Badari Atreya ,  Ravindran Suresh

IPC: G06F9/44 ,  G06F9/45 ,  G06F15/76 ,  G06F15/78 ,  G06F9/30

CPC classification number: G06F8/33 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/445 ,  G06F8/447 ,  G06F8/451 ,  G06F8/70 ,  G06F9/30145 ,  G06F15/76 ,  G06F15/7825

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

公开(公告)号：US09864583B2

公开(公告)日：2018-01-09

申请号：US14675692

申请日：2015-03-31

Applicant: CAVIUM, INC.

Inventor： Ajeer Salil Pudiyapura ,  Kishore Badari Atreya ,  Ravindran Suresh

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/30 ,  G06F15/78 ,  G06F15/76

CPC classification number: G06F8/33 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/445 ,  G06F8/447 ,  G06F8/451 ,  G06F8/70 ,  G06F9/30145 ,  G06F15/76 ,  G06F15/7825

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

公开(公告)号：US09747088B2

公开(公告)日：2017-08-29

申请号：US14082005

申请日：2013-11-15

Applicant: Embarcadero Technologies, Inc.

Inventor： Allen Bauer

IPC: G06F9/45 ,  G06F12/02

CPC classification number: G06F8/4434 ,  G06F12/0261

Abstract: Methods for enabling automatic reference counting are disclosed. A source code is searched for a particular pattern via a compiler associated with a computer system, wherein the source code is written in an existing language and wherein the particular pattern is for a reference associating an object with a portion of memory. The particular pattern is recognized at the computer system. The particular pattern is replaced with an automatic reference counting implementation at the computer system. The source code is executed with the automatic reference counting implementation.