公开(公告)号：US20240329948A1

公开(公告)日：2024-10-03

申请号：US18129288

申请日：2023-03-31

申请人： International Business Machines Corporation

发明人： Zhong Fang Yuan ,  Tong Liu ,  Han Qiao Yu ,  Lin Feng ,  Xiang Yu Yang ,  Hai Bo Zou

IPC分类号： G06F8/41 ,  G06F8/71 ,  G06N20/00

CPC分类号： G06F8/427 ,  G06F8/4441 ,  G06F8/71 ,  G06N20/00

摘要： A given segment of computer code is obtained and modified to produce one or more inefficient versions of the given segment of computer code in comparison to the given segment of computer code. A code parse tree is generated for the given segment of computer code and each inefficient version of the given segment of computer code. Model embeddings are generated based on the generated code parse trees and a diffusion model is trained based on the generated model embeddings.

公开(公告)号：US20240311112A1

公开(公告)日：2024-09-19

申请号：US18185413

申请日：2023-03-17

申请人： dSPACE GmbH

发明人： Joerg Niere ,  Kingshuk Karuri ,  Pubali Mazumder

IPC分类号： G06F8/41

CPC分类号： G06F8/456 ,  G06F8/4441

摘要： A method for generating source code includes: transforming a block diagram into an intermediate representation, wherein transforming the block diagram into the intermediate representation comprises transforming at least two blocks, wherein at least one loop results from transforming an operation block; identifying at least one candidate loop in the intermediate representation, wherein a loop body of a candidate loop comprises at least one instruction that accesses the array variable; identifying at least one parallelizable loop from the at least one candidate loop; determining build options for the at least one parallelizable loop and the array variable; inserting build pragmas based on the determined build options in the intermediate representation; and translating the intermediate representation into the source code.

公开(公告)号：US12093691B2

公开(公告)日：2024-09-17

申请号：US17795952

申请日：2020-02-14

申请人： NEC Corporation

发明人： Yoshiyuki Ohno

IPC分类号： G06F9/44 ,  G06F9/06 ,  G06F9/30 ,  G06F9/32 ,  G06F8/40 ,  G06F8/41

CPC分类号： G06F9/325 ,  G06F9/3001 ,  G06F8/40 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/452

摘要： A generation unit generates arithmetic expressions. Here, N denotes the number of looping times of the loop processing. L denotes a designated lower limit of unroll stage number. M denotes a designated upper limit of the unroll stage number. Q denotes a quotient obtained by dividing N by L. R denotes a remainder obtained by dividing N by L. The arithmetic expressions include an arithmetic expression that represents executing loop processing whose number of looping times is a quotient obtained by dividing R by (M−L), with the unroll stage number M when R−Q*(M−L)>0 is not satisfied, and then executing, when a remainder obtained by dividing R by (M−L) is other than 0, processing of one loop with sum of the remainder and L as the unroll stage number, and then executing loop processing with the unroll stage number L.

公开(公告)号：US12051006B2

公开(公告)日：2024-07-30

申请号：US17903991

申请日：2022-09-06

申请人： Apple Inc.

发明人： Gaurav Kapoor ,  Cecile M. Foret ,  Francesco Rossi ,  Kit-Man Wan ,  Umesh S. Vaishampayan ,  Etienne Belanger ,  Albert Antony ,  Alexey Marinichev ,  Marco Zuliani ,  Xiaojin Shi

IPC分类号： G06N3/10 ,  G06F8/41 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

CPC分类号： G06N3/10 ,  G06F8/41 ,  G06F8/443 ,  G06F8/4441 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F9/50 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06N3/10

摘要： The subject technology provides receiving a neural network (NN) model to be executed on a target platform, the NN model including multiple layers that include operations and some of the operations being executable on multiple processors of the target platform. The subject technology further sorts the operations from the multiple layers in a particular order based at least in part on grouping the operations that are executable by a particular processor of the multiple processors. The subject technology determines, based at least in part on a cost of transferring the operations between the multiple processors, an assignment of one of the multiple processors for each of the sorted operations of each of the layers in a manner that minimizes a total cost of executing the operations. Further, for each layer of the NN model, the subject technology includes an annotation to indicate the processor assigned for each of the operations.

公开(公告)号：US20240201968A1

公开(公告)日：2024-06-20

申请号：US18407383

申请日：2024-01-08

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Zhikang Liu ,  Lingfei Wu ,  Jinglei Lu ,  Ziming Xu ,  Chen Cheng

IPC分类号： G06F8/41

CPC分类号： G06F8/4441

摘要： This application discloses a program compilation method including: obtaining a first program, where the first program includes a plurality of layers of loop statements, a loop condition of each layer of loop statement in the plurality of layers of loop statements includes a variable and a value interval of the variable, and a loop body of the plurality of layers of loop statements includes at least one conditional statement; processing a value interval of a first variable in a first loop statement included in the plurality of layers of loop statements, to obtain a second loop statement; and compiling the first program based on at least one loop statement to obtain a compilation result of the first program.

公开(公告)号：US20240094999A1

公开(公告)日：2024-03-21

申请号：US17948425

申请日：2022-09-20

申请人： International Business Machines Corporation

发明人： Kazuaki Ishizaki

IPC分类号： G06F8/41 ,  G06F9/38

CPC分类号： G06F8/4441 ,  G06F9/3887

摘要： A computer-implemented method, system and computer program product for improving the performance of a program that manipulates two vectors of data. It is determined whether the program contains one of the following patterns: a first pattern corresponding to v0.rearrange(s, v1); a second pattern corresponding to v0.blend(v1, m); and a third pattern corresponding to v0.rearrange(s).blend(v1.rearrange(s), m). Upon identifying code written as the first pattern in the program, the first pattern is rewritten and replaced with the second or third pattern if the execution time of the program with the second or third pattern is less than the execution time of the program with the first program. In a similar manner, upon identifying code written as the second or third pattern in the program, the second or third pattern is rewritten and replaced with the first pattern if the execution time of the program can be improved.

公开(公告)号：US11934813B2

公开(公告)日：2024-03-19

申请号：US17456426

申请日：2021-11-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Wai Hung Tsang ,  Ettore Tiotto

IPC分类号： G06F8/41

CPC分类号： G06F8/4441

摘要： Early exit of a loop is performed. A determination is made as to whether a loop within computer code reaches a fixed point of processing, which is predefined. Based on determining that the loop reaches the fixed point of processing, at least one indication is included in the loop to perform an early exit of the loop prior to a last iteration of the loop.

公开(公告)号：US11907549B2

公开(公告)日：2024-02-20

申请号：US17357723

申请日：2021-06-24

申请人： QUALCOMM Incorporated

发明人： Muthu Manikandan Baskaran ,  Thomas Henretty ,  Ann Johnson ,  Athanasios Konstantinidis ,  M. H. Langston ,  Janice O. Mcmahon ,  Benoit J. Meister ,  Paul D. Mountcastle ,  Aale Naqvi ,  Benoit Pradelle ,  Tahina Ramananandro ,  Sanket Tavarageri ,  Richard A. Lethin

IPC分类号： G06F3/06 ,  G06F8/41

CPC分类号： G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0671 ,  G06F8/4432 ,  G06F8/4441 ,  G06F8/453 ,  Y02D10/00

摘要： A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.

公开(公告)号：US11846974B2

公开(公告)日：2023-12-19

申请号：US17571130

申请日：2022-01-07

申请人： TACHYUM LTD.

发明人： Radoslav Danilak

IPC分类号： G06F15/78 ,  G06F9/38 ,  G06F9/30 ,  G06F7/57 ,  G06F16/901 ,  G06F8/41

CPC分类号： G06F15/78 ,  G06F9/3869 ,  G06F7/57 ,  G06F8/433 ,  G06F8/443 ,  G06F8/4441 ,  G06F9/30007 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3889 ,  G06F16/9024

摘要： A processor has first, second and third ALUs. The first ALU has on a first side an input and an output. The second ALU has a first side facing the first side of the first ALU, an input and an output on the first side of the second ALU and being in a rotated orientation relative to the input and the output of the first side of the first ALU, and an output on a second side of the second ALU. The third ALU has a first side facing the second side of the second ALU, and an input and an output on the first side of the third ALU. The input of the first side of the first ALU is logically directly connected to the output of the first side of the second ALU.

公开(公告)号：US11829758B2

公开(公告)日：2023-11-28

申请号：US18120532

申请日：2023-03-13

申请人： Micron Technology, Inc.

发明人： Skyler Arron Windh ,  Gongyu Wang

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F8/41

CPC分类号： G06F9/30058 ,  G06F8/4441 ,  G06F8/451 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/3838

摘要： Disclosed in some examples, are systems, methods, devices, and machine readable mediums which use improved dynamic programming algorithms to pack conditional branch instructions. Conditional code branches may be modeled as directed acyclic graphs (DAGs) which have a topological ordering. These DAGs may be used to construct a dynamic programming table to find a partial mapping of one path onto the other path using dynamic programming algorithms.