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    METHOD OF REORDERING CONDITION CHECKS
    3.
    发明申请
    METHOD OF REORDERING CONDITION CHECKS 审中-公开

    公开(公告)号：US20190188113A1

    公开(公告)日：2019-06-20

    申请号：US16285781

    申请日：2019-02-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Takuya Nakaike ,  Takeshi Ogasawara

    IPC: G06F11/36 ,  G06F8/41

    CPC classification number: G06F11/3608 ,  G06F8/4441 ,  G06F8/45 ,  G06F8/458 ,  G06F11/3612 ,  G06F11/3644 ,  G06F11/3664

    Abstract: Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code are identified. It is determined that the execution frequency of a later one of the condition checks is satisfied at a greater frequency than a preceding one of the condition checks. It is determined that there is an absence of side effects in the two or more condition checks. The values of the condition checks are propagated and abstract interpretation is performed on the values that are propagated. It is determined that the condition checks are exclusive of each other, and the condition checks are reordered within the computer code.

    DYNAMIC ALIAS CHECKING WITH TRANSACTIONAL MEMORY
    4.
    发明申请
    DYNAMIC ALIAS CHECKING WITH TRANSACTIONAL MEMORY 审中-公开

    公开(公告)号：US20180095736A1

    公开(公告)日：2018-04-05

    申请号：US15850668

    申请日：2017-12-21

    Applicant: International Business Machines Corporation

    Inventor： Yaoqing Gao ,  William G. O'Farrell ,  Denis Palmeiro

    IPC: G06F9/45 ,  G06F9/52 ,  G06F9/46

    CPC classification number: G06F8/434 ,  G06F8/41 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/4441 ,  G06F8/458 ,  G06F9/467 ,  G06F9/52

    Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.

    DATA PROCESSING SYSTEMS
    8.
    发明申请
    DATA PROCESSING SYSTEMS 审中-公开

    公开(公告)号：US20170206698A1

    公开(公告)日：2017-07-20

    申请号：US15401639

    申请日：2017-01-09

    Applicant: ARM Limited

    Inventor： Sean Tristram LeGuay Ellis ,  Thomas James Cooksey ,  Robert Martin Elliott

    IPC: G06T15/00 ,  G06T15/80

    CPC classification number: G06T15/005 ,  G06F8/41 ,  G06F8/454 ,  G06F8/458 ,  G06T15/80

    Abstract: A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being executed by the execution unit, and where the register(s) assigned to an individual execution thread are accessible only to that associated individual execution thread, and a further local memory that is operable to store data for use in common by plural execution threads, where the data stored in the further local memory is accessible to plural execution threads as they execute. The programmable execution unit is operable to selectively store output data for an execution thread in a register(s) of the local register memory assigned to the execution thread, and the further local memory.

    Language-based model for asynchronous operations
    9.
    发明授权
    Language-based model for asynchronous operations 有权

    公开(公告)号：US09690604B2

    公开(公告)日：2017-06-27

    申请号：US15408011

    申请日：2017-01-17

    Applicant: Microsoft Technology Licensing, LLC

    Inventor： Niklas Gustafsson ,  Geoffrey M. Kizer

    IPC: G06F9/44 ,  G06F9/45 ,  G06F9/455

    CPC classification number: G06F9/45516 ,  G06F8/40 ,  G06F8/41 ,  G06F8/45 ,  G06F8/458

    Abstract: A language-based model to support asynchronous operations set forth in a synchronous syntax is provided. The asynchronous operations are transformed in a compiler into an asynchronous pattern, such as an APM-based pattern (or asynchronous programming model based pattern). The ability to compose asynchronous operations comes from the ability to efficiently call asynchronous methods from other asynchronous methods, pause them and later resume them, and effectively implementing a single-linked stack. One example includes support for ordered and unordered compositions of asynchronous operations. In an ordered composition, each asynchronous operation is started and finished before another operation in the composition is started. In an unordered composition, each asynchronous operation is started and completed independently of the operations in the unordered composition.

    Techniques for Enhancing Progress for Hardware Transactional Memory
    10.
    发明申请
    Techniques for Enhancing Progress for Hardware Transactional Memory 审中-公开
    增强硬件事务性内存进度的技术

    公开(公告)号：US20170046182A1

    公开(公告)日：2017-02-16

    申请号：US15221428

    申请日：2016-07-27

    Applicant: Oracle International Corporation

    Inventor： Alex Kogan ,  David Dice ,  Maurice P. Herlihy

    IPC: G06F9/445

    CPC classification number: G06F9/466 ,  G06F8/458 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/44552 ,  G06F9/46 ,  G06F9/467 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4812 ,  G06F9/4831 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/5038 ,  G06F9/52 ,  G06F9/526

    Abstract: Hardware transactional memory (HTM) systems may guarantee that transactions commit without falling back to non-speculative code paths. A transaction that fails to progress may enter a power mode, giving the transaction priority when it conflicts with non-power-mode transactions. If, during execution of a power-mode transaction, another thread attempts, using a non-power-mode transaction, to access a shared resource being accessed by the power-mode transaction, it may be determined whether any actual data conflict occurs between the two transactions. If no data conflict exists, both transactions may continue to completion. If, however, a data conflict does exist, the power-mode transaction may deny the other transaction access to the shared resource. HTM systems may, in some embodiments, ensure that only one power-mode transaction exists at a time. In other embodiments, multiple, concurrent, power-mode transactions may be supported while ensuring that they access disjoint data sets.

    Abstract translation: 硬件事务存储器（HTM）系统可以保证事务提交而不会退回到非推测性代码路径。 无法进行的事务可能进入电源模式，当与非电源模式事务冲突时，优先处理事务。 如果在执行功率模式事务期间，另一线程使用非功率模式事务尝试访问由功率模式事务访问的共享资源，则可以确定是否在任何实际的数据冲突之间发生任何实际的数据冲突 两笔交易。 如果不存在数据冲突，则两个事务都可能继续完成。 然而，如果确实存在数据冲突，则功率模式事务可以拒绝其他事务对共享资源的访问。 在一些实施例中，HTM系统可以确保一次只存在一个功率模式事务。 在其他实施例中，可以支持多个并发的功率模式事务，同时确保它们访问不相交的数据集。

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