公开(公告)号：US12130735B2

公开(公告)日：2024-10-29

申请号：US18147362

申请日：2022-12-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wei Fang ,  Xie Miao ,  Tao Hou

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F13/1668 ,  G06F2212/7201

Abstract: Data writing methods and computing devices are provided. An example data writing method is applied to a computer system, and the computer system includes a file system and a flash memory-based storage system. The example data writing method includes obtaining a target logical address, where the target logical address is an address allocated from a first logical block to target data to be written into the flash memory-based storage system, the first logical block is one of multiple logical blocks in the file system, and the flash memory-based storage system includes multiple physical blocks. It is determined that the target logical address belongs to the first logical block. The target data is written into a first physical block based on a correspondence between the first logical block and the first physical block, where the first physical block is one of the multiple physical blocks.

公开(公告)号：US12124370B2

公开(公告)日：2024-10-22

申请号：US17849810

申请日：2022-06-27

Applicant: KIOXIA CORPORATION

Inventor： Shinichi Kanno

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C29/00

CPC classification number: G06F12/06 ,  G06F3/06 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G11C29/82 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.

公开(公告)号：US20240345990A1

公开(公告)日：2024-10-17

申请号：US18626775

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Varghese George ,  Ben Ashbaugh ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek Appu ,  Nicolas Galoppo Von Borries ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Nilay Mistry ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur Shah ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

公开(公告)号：US20240345772A1

公开(公告)日：2024-10-17

申请号：US18616970

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Roberto Izzi ,  Nicola Colella ,  Luca Porzio ,  Marco Onorato

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

公开(公告)号：US20240345751A1

公开(公告)日：2024-10-17

申请号：US18299354

申请日：2023-04-12

Applicant: Dell Products L.P.

Inventor： Bruce E. Caram ,  Vamsi K. Vankamamidi ,  Alexei Karaban ,  Ajay Karri

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0608 ,  G06F3/0665 ,  G06F3/067 ,  G06F12/0246

Abstract: A technique consolidates data at multiple levels of granularity, the levels including a first level based on whole PLBs (physical large blocks) and a second level based on portions of donor PLBs. The technique further includes tracking PLBs in multiple PLB queues arranged based on storage utilization of the PLBs, and tracking PLB portions in multiple portion queues arranged based on storage utilization of the portions. When consolidating data to create a new PLB, a set of whole PLBs is selected, based on utilization, from the PLB queues, and a set of portions of donor PLBs is selected, based on utilization, from the portion queues. The selections are performed such that the total data size of the selected whole PLB(s) and the selected portion(s) fit within the new PLB.

公开(公告)号：US20240339159A1

公开(公告)日：2024-10-10

申请号：US18745660

申请日：2024-06-17

Applicant: PURE STORAGE, INC.

Inventor： ZOLTAN DEWITT ,  BENJAMIN SCHOLBROCK ,  ANDREW BERNAT ,  RONALD KARR ,  ROBERT LEE

IPC: G11C16/16 ,  G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G06F16/174

CPC classification number: G11C16/16 ,  G06F3/064 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0689 ,  G06F11/1076 ,  G06F12/0246 ,  G06F12/0253 ,  G06F16/1752

Abstract: Allocation units having equal allocation unit sizes are formed for writing into erase blocks of a storage system. One or more of the allocation units are formed of at least a portion of two erase blocks. Data is written to the erase blocks forming the allocation units such that one of the erase blocks is open at a time during the writing of the data.

公开(公告)号：US12111759B2

公开(公告)日：2024-10-08

申请号：US17846524

申请日：2022-06-22

Applicant: BEIJING MEMBLAZE TECHNOLOGY CO., LTD

Inventor： Yingyi Ju ,  Rong Yuan ,  Baoyong Sun ,  Zhihong Guo ,  Huijuan Gao ,  Shunan Cai

IPC: G06F12/02 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F12/0246 ,  G06F9/3885 ,  G06F9/5016 ,  G06F9/5022 ,  G06F12/0253 ,  G06F12/0292 ,  G06F2212/7201

Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.

公开(公告)号：US20240330177A1

公开(公告)日：2024-10-03

申请号：US18615069

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Meng Wei ,  Tom V. Geukens

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0292 ,  G06F12/0246 ,  G06F13/1626 ,  G06F2212/7201

Abstract: Aspects of the present disclosure configure a memory sub-system controller to fold data based on valid translational unit count (VTC) values in a memory sub-system. The controller receives a request to perform a folding operation on data stored in an individual block stripe of the set of memory components. The controller retrieves, from a VTC table, a plurality of VTC values corresponding to a plurality of portions of the individual block stripe. The controller compares a first VTC value of the plurality of VTC values associated with a first of the plurality of portions to a second VTC value of the plurality of VTC values associated with a second of the plurality of portions. The controller performs the folding operation on a subset of the plurality of portions based on a result of comparing the first VTC value to the second VTC value.

公开(公告)号：US20240330174A1

公开(公告)日：2024-10-03

申请号：US18608251

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Shawn Storm ,  Joseph A. Oberle ,  Ji-Hye Gale Shin

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A method includes configuring a memory system with a first set of operating characteristics corresponding to a first thermal voltage model, monitoring operation of the memory system, selecting a second thermal voltage model based on the monitored operation of the memory system, configuring the memory system with a second set of operating characteristics corresponding to the second thermal voltage model, and writing data to the memory system configured with the second set of operating characteristics.

公开(公告)号：US20240330173A1

公开(公告)日：2024-10-03

申请号：US18192561

申请日：2023-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Radu Ioan STOICA ,  Dan LAZAR ,  Timothy J. FISHER ,  Nikolaos PAPANDREOU ,  Roman Alexander PLETKA ,  Charalampos POZIDIS ,  Aaron Daniel FRY ,  Andrew D. WALLS

IPC: G06F12/02 ,  G06F12/0802

CPC classification number: G06F12/0246 ,  G06F12/0802 ,  G06F2212/45 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207

Abstract: A controller of the solid-state drive (SSD) maintains a logical-to-physical translation layer, wherein metadata for the logical-to-physical translation layer is stored in metadata pages in a flash memory of the SSD. The controller tracks a write heat of the metadata pages. The controller stores relatively more frequently accessed metadata pages in a non-durable cache of the SSD. The controller prioritized metadata write operations based on write heat of the metadata pages, such that a NAND flash block of the flash memory contains metadata pages with a similar write heat, wherein extents with similar write heats are grouped together into a stripe that stores extent data, and wherein write heats of the extents with the similar write heats do not differ from each other beyond a predetermined threshold.