公开(公告)号：US20240320184A1

公开(公告)日：2024-09-26

申请号：US18620284

申请日：2024-03-28

申请人： Intel Corporation

发明人： Altug Koker ,  Ben Ashbaugh ,  Scott Janus ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Niranjan Cooray ,  Varghese George ,  Arthur Hunter ,  Brent E. Insko ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC分类号： G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：US12099461B2

公开(公告)日：2024-09-24

申请号：US17431034

申请日：2020-03-14

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayanan Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC分类号： G06F16/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

公开(公告)号：US11899614B2

公开(公告)日：2024-02-13

申请号：US17849201

申请日：2022-06-24

申请人： Intel Corporation

发明人： Joydeep Ray ,  Altug Koker ,  Varghese George ,  Mike Macpherson ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Nicolas Galoppo von Borries ,  Ben J. Ashbaugh

IPC分类号： G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F17/18 ,  G06F12/0802 ,  G06F7/544 ,  G06F7/575 ,  G06F12/02 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F12/0811 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06F12/0871 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/50 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0888 ,  G06T15/06 ,  G06N3/08

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

公开(公告)号：US11757468B2

公开(公告)日：2023-09-12

申请号：US17334688

申请日：2021-05-29

申请人： SANDISK TECHNOLOGIES LLC

发明人： Nihal Singla ,  A Harihara Sravan

IPC分类号： H03M7/46 ,  H03M7/30 ,  G06F3/06 ,  H03M7/42

CPC分类号： H03M7/6011 ,  G06F3/0659 ,  H03M7/42

摘要： An encoder of a storage medium encodes data subject to a read operation specified by a storage controller by generating a plurality of symbols representing a soft data stream corresponding to the data subject to the read operation, where each symbol of the plurality of symbols includes (i) a single-bit value number indicating whether the symbol counts 0s or 1s, and (ii) an N-bit count number indicating a bit count associated with the symbol, where N is greater than or equal to two, and the encoder of the storage medium is configured to convey the plurality of generated symbols to the storage controller via electrical interface circuitry connecting the storage medium and the storage controller.

公开(公告)号：US20230283294A1

公开(公告)日：2023-09-07

申请号：US17941376

申请日：2022-09-09

申请人： Kioxia Corporation

发明人： Youhei FUKAZAWA ,  Keiri NAKANISHI ,  Sho KODAMA

IPC分类号： H03M7/30 ,  H03M7/46

CPC分类号： H03M7/3088 ,  H03M7/46

摘要： According to one embodiment, an information processing apparatus includes a processor. The processor divides teacher data into character strings, calculates a score of each of the character strings based on at least an appearance frequency of each character string in the character strings, an appearance position of each of the character string in the character strings, and a length of each of the character strings, and determines a position of each of the character strings in a preset dictionary based on the score.

公开(公告)号：US11722149B2

公开(公告)日：2023-08-08

申请号：US17899993

申请日：2022-08-31

申请人： Beijing Tenafe Electronic Technology Co., Ltd.

发明人： Yingquan Wu

IPC分类号： H03M7/42 ,  H03M7/30 ,  H03M7/46 ,  H03M7/40

CPC分类号： H03M7/42 ,  H03M7/3086 ,  H03M7/405 ,  H03M7/46 ,  H03M7/6005

摘要： An input sequence that has a plurality of bits is received where the input sequence is associated with a first section of data within a compressed block. The plurality of bits in the input sequence are divided into a first sub-sequence comprising a first set of bits and a second sub-sequence comprising a second set of bits. The first sub-sequence is encoded using a first Huffman code tree to obtain a first codeword and the second sub-sequence is encoded using a second Huffman code tree to obtain a second codeword. Encoded data that includes information associated with the first Huffman code tree, information associated with the second Huffman code tree, the first codeword, and the second codeword is output.

公开(公告)号：US11632129B2

公开(公告)日：2023-04-18

申请号：US17965141

申请日：2022-10-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hoyoung Kim

IPC分类号： H03M7/00 ,  H03M7/30 ,  G06N3/02 ,  H03M7/46 ,  H03M7/40 ,  G06N3/063 ,  G06N3/082

摘要： A method of compressing weights of a neural network includes compressing a weight set including the weights of a the neural network, determining modified weight sets by changing at least one of the weights, calculating compression efficiency values for the determined modified weight sets based on a result of compressing the weight set and results of compressing the determined modified weight sets, determining a target weight of the weights satisfying a compression efficiency condition among the weights based on the calculated compression efficiency values, and determining a final compression result by compressing the weights based on a result of replacing the determined target weight.

公开(公告)号：US11528033B2

公开(公告)日：2022-12-13

申请号：US15953356

申请日：2018-04-13

申请人： Microsoft Technology Licensing, LLC

发明人： Joseph Leon Corkery ,  Benjamin Eliot Lundell ,  Larry Marvin Wall ,  Chad Balling McBride ,  Amol Ashok Ambardekar ,  George Petre ,  Kent D. Cedola ,  Boris Bobrov

IPC分类号： H03M7/30 ,  G06N3/04 ,  G06N3/063 ,  G06F12/0862 ,  G06F9/46 ,  G06F1/324 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F17/15 ,  G06N3/06 ,  G06N3/08 ,  G06N3/10 ,  H04L45/02 ,  H04L67/02 ,  G06F9/30 ,  H04L67/1001 ,  G06F9/48 ,  G06F12/02 ,  G06F13/16 ,  G06F1/3234 ,  G06F13/28 ,  H03M7/46 ,  H04L45/50

摘要： A deep neural network (“DNN”) module compresses and decompresses neuron-generated activation data to reduce the utilization of memory bus bandwidth. The compression unit receives an uncompressed chunk of data generated by a neuron in the DNN module. The compression unit generates a mask portion and a data portion of a compressed output chunk. The mask portion encodes the presence and location of the zero and non-zero bytes in the uncompressed chunk of data. The data portion stores truncated non-zero bytes from the uncompressed chunk of data. A decompression unit receives a compressed chunk of data from memory in the DNN processor or memory of an application host. The decompression unit decompresses the compressed chunk of data using the mask portion and the data portion.

公开(公告)号：US11502701B2

公开(公告)日：2022-11-15

申请号：US17394584

申请日：2021-08-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hoyoung Kim

IPC分类号： H03M7/00 ,  H03M7/30 ,  G06N3/02 ,  H03M7/46 ,  H03M7/40 ,  G06N3/063 ,  G06N3/08

摘要： A method of compressing weights of a neural network includes compressing a weight set including the weights of a the neural network, determining modified weight sets by changing at least one of the weights, calculating compression efficiency values for the determined modified weight sets based on a result of compressing the weight set and results of compressing the determined modified weight sets, determining a target weight of the weights satisfying a compression efficiency condition among the weights based on the calculated compression efficiency values, and determining a final compression result by compressing the weights based on a result of replacing the determined target weight.

公开(公告)号：US11341399B2

公开(公告)日：2022-05-24

申请号：US15953195

申请日：2018-04-13

申请人： Microsoft Technology Licensing, LLC

发明人： Amol Ashok Ambardekar ,  Chad Balling McBride ,  George Petre ,  Larry Marvin Wall ,  Kent D. Cedola ,  Boris Bobrov

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06N3/10 ,  G06F12/0862 ,  G06F9/46 ,  G06F1/324 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F17/15 ,  G06N3/06 ,  H03M7/30 ,  H04L45/00 ,  H04L67/02 ,  H04L67/1001 ,  G06F9/30 ,  G06F13/16 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/28 ,  H03M7/46 ,  H04L45/50

摘要： A deep neural network (“DNN”) module can determine whether processing of certain values in an input buffer or a weight buffer by neurons can be skipped. For example, the DNN module might determine whether neurons can skip the processing of values in entire columns of a neuron buffer. Processing of these values might be skipped if an entire column of an input buffer or a weight buffer are zeros, for example. The DNN module can also determine whether processing of single values in rows of the input buffer or the weight buffer can be skipped (e.g. if the values are zero). Neurons that complete their processing early as a result of skipping operations can assist other neurons with their processing. A combination operation can be performed following the completion of processing that transfers the results of the processing operations performed by a neuron to their correct owner.