公开(公告)号：US12236153B2

公开(公告)日：2025-02-25

申请号：US18507741

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duk Ki Hong ,  Hyuk Kang ,  Jeong Hun Kim ,  Jae Bong Yoo ,  Kyung Soo Lim ,  Jun Hak Lim ,  Min Gyew Kim ,  Na Jung Seo

IPC: G06T1/20 ,  G06F3/14 ,  G09G5/00 ,  H04M1/724 ,  H04M1/02

Abstract: An electronic device is provided that includes a first display and a second display. The electronic device also includes a processor configured to allocate a first set of resources to the first display and a second set of resources to the second display. The first set of resources is different from the second set of resources. Each of the first set of resources and the second set of resources includes one or more of at least one available hardware resource and at least one available software resource.

公开(公告)号：US20250061534A1

公开(公告)日：2025-02-20

申请号：US18819073

申请日：2024-08-29

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

公开(公告)号：US12229870B2

公开(公告)日：2025-02-18

申请号：US17982766

申请日：2022-11-08

Applicant: INTEL CORPORATION

Inventor： Michael Apodaca ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Timothy Rowley ,  Joshua Barczak ,  Travis Schluessler

IPC: G06T15/06 ,  G06F7/14 ,  G06F9/38 ,  G06F16/901 ,  G06N3/02 ,  G06T1/20 ,  G06T1/60 ,  G06T5/70

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US12229851B2

公开(公告)日：2025-02-18

申请号：US18385265

申请日：2023-10-30

Applicant: Imagination Technologies Limited

Inventor： Rudi Bonfiglioli ,  Richard Broadhurst

IPC: G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T17/10

Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.

公开(公告)号：US12229581B2

公开(公告)日：2025-02-18

申请号：US18239489

申请日：2023-08-29

Applicant: INTEL CORPORATION

Inventor： Rajesh Sankaran ,  Bret Toll ,  William Rash ,  Subramaniam Maiyuran ,  Gang Chen ,  Varghese George

IPC: G06F9/455 ,  G06F12/1009 ,  G06T1/20

Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics processing apparatuses connected using a scale-up fabric, provision the scale-up fabric to route data within the subcluster of graphics processing apparatuses, and provision a plurality of resources on the graphics processing apparatus for the subcluster based on the request from the VMM.

公开(公告)号：US12229569B2

公开(公告)日：2025-02-18

申请号：US18384714

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Liu Yang ,  Anbang Yao

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06T15/00

Abstract: Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

公开(公告)号：US20250054222A1

公开(公告)日：2025-02-13

申请号：US18779641

申请日：2024-07-22

Applicant: Sony Interactive Entertainment LLC

Inventor： Mark Evan Cerny

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06T15/80

Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

公开(公告)号：US20250054109A1

公开(公告)日：2025-02-13

申请号：US18929660

申请日：2024-10-29

Applicant: GRAVITYXR ELECTRONICS AND TECHNOLOGY CO., LTD.

Inventor： Jinfeng ZHAN ,  Rui ZHANG ,  Tao JIA ,  Chaohao WANG

IPC: G06T5/50 ,  G06T1/20

Abstract: A data transmission method includes: acquiring data of a display image layer and data of a transparency layer and determining, based on the data of the display image layer and the data of the transparency layer, multiple sets of data to be superimposed; constructing a target layer based on the display image layer and the transparency layer for each set of data to be superimposed; determining first placement data and second placement data of the corresponding target layer based on the data of the display image layer and the data of the transparency layer for each set of data to be superimposed; placing the first placement data to a first position of the corresponding target layer and placing the second placement data to a second position of the corresponding target layer, to obtain data of the corresponding target layer; and transmitting data of multiple target layers.

公开(公告)号：US12223682B2

公开(公告)日：2025-02-11

申请号：US17357038

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Stephen Junkins ,  Sreenivas Kothandaraman ,  Prasoonkumar Surti ,  Srihari Pratapa ,  William Hux ,  John Feit

IPC: G06T9/00 ,  G06T1/20 ,  G06T1/60

Abstract: Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.

公开(公告)号：US12223585B2

公开(公告)日：2025-02-11

申请号：US18376098

申请日：2023-10-03

Applicant: INTEL CORPORATION

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/06 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.