公开(公告)号：US20240282045A1

公开(公告)日：2024-08-22

申请号：US18589239

申请日：2024-02-27

申请人： Intel Corporation

发明人： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC分类号： G06T15/06 ,  G06T15/00

CPC分类号： G06T15/06 ,  G06T15/005 ,  G06T2210/21

摘要： An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US20240281249A1

公开(公告)日：2024-08-22

申请号：US18170808

申请日：2023-02-17

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Karthik Vaidyanathan ,  Sreedhar Chalasani ,  Eric Liskay ,  Prathamesh Raghunath Shinde ,  Vasanth Ranganathan ,  Michael J. Norris ,  Rajasekhar Pantangi

IPC分类号： G06F9/30 ,  G06F9/54

CPC分类号： G06F9/30043 ,  G06F9/30047 ,  G06F9/546

摘要： One embodiment provides a graphics processor comprising memory access circuitry configured to receive a message from an instruction execution resource and determine a destination for the message, the destination one of shared function circuitry of a graphics core or a set of memory banks within the graphics core. The memory access circuitry then routes the message to the shared function circuitry in response to a determination that the message is directed to the shared function circuitry or routes the message to a message sequencer associated with the instruction execution resource in response to a determination that the message is directed to the set of memory banks.

公开(公告)号：US20240161356A1

公开(公告)日：2024-05-16

申请号：US18517318

申请日：2023-11-22

申请人： Intel Corporation

发明人： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC分类号： G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC分类号： G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

摘要： Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US11983791B2

公开(公告)日：2024-05-14

申请号：US17019479

申请日：2020-09-14

申请人： Intel Corporation

发明人： Sreenivas Kothandaraman ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Karol Szerszen ,  Prasoonkumar Surti

IPC分类号： G06T1/20 ,  G06F9/38 ,  G06F16/907 ,  G06T7/90

CPC分类号： G06T1/20 ,  G06F9/3838 ,  G06F9/3877 ,  G06F16/907 ,  G06T7/90

摘要： An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.

公开(公告)号：US11915369B2

公开(公告)日：2024-02-27

申请号：US16819120

申请日：2020-03-15

申请人： Intel Corporation

发明人： Karthik Vaidyanathan ,  Carsten Benthin ,  Sven Woop

IPC分类号： G06T15/00 ,  G06T15/06 ,  G06T15/08 ,  G06T17/20 ,  G06T17/10 ,  G06F7/24 ,  G06T1/20

CPC分类号： G06T17/10 ,  G06F7/24 ,  G06T1/20 ,  G06T15/005 ,  G06T15/06 ,  G06T15/08 ,  G06T17/205

摘要： Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.

公开(公告)号：US11887243B2

公开(公告)日：2024-01-30

申请号：US17533341

申请日：2021-11-23

申请人： INTEL CORPORATION

发明人： Karthik Vaidyanathan ,  Sven Woop ,  Carsten Benthin

IPC分类号： G06T15/06 ,  G06T1/60 ,  G06T9/40 ,  G06T17/00

CPC分类号： G06T15/06 ,  G06T1/60 ,  G06T9/40 ,  G06T17/005 ,  G06T2210/12 ,  G06T2210/21

摘要： Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.

公开(公告)号：US20230090973A1

公开(公告)日：2023-03-23

申请号：US17480528

申请日：2021-09-21

申请人： Intel Corporation

发明人： Joydeep Ray ,  Abhishek R. Appu ,  Timothy R. Bauer ,  James Valerio ,  Weiyu Chen ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Sven Woop ,  Jiasheng Chen

IPC分类号： G06F9/30 ,  G06F12/02 ,  G06F13/16

摘要： One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

公开(公告)号：US11593910B2

公开(公告)日：2023-02-28

申请号：US17741934

申请日：2022-05-11

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06N3/063 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/084 ,  G06F8/41

摘要： Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US11568591B2

公开(公告)日：2023-01-31

申请号：US16996208

申请日：2020-08-18

申请人： INTEL CORPORATION

发明人： Karthik Vaidyanathan ,  Michael Apodaca ,  Thomas Raoux ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Joshua Barczak

IPC分类号： G06T15/06 ,  G06T1/60 ,  G06T5/00 ,  G06T9/00

摘要： An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US11562461B2

公开(公告)日：2023-01-24

申请号：US17529862

申请日：2021-11-18

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06T15/80 ,  G06F3/14 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.