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公开(公告)号：US11948017B2
公开(公告)日：2024-04-02
申请号：US16896031
申请日：2020-06-08
申请人： Intel Corporation
发明人： Abhishek Venkatesh , Michael Apodaca , Stav Gurtovoy , John H. Feit , Mateusz Przybylski , David M. Cimini
摘要： Examples described herein relate to a graphics processing apparatus that includes a memory device; and a central processing unit (CPU). In some examples, the CPU is configured to: execute a producer to issue graphics command application program interfaces (APIs); execute a driver to translate graphics command APIs into executable instructions; and based on an idle state of the producer, execute a command translation code segment of the producer to translate graphics command APIs into executable instructions. In some examples, the execution unit is coupled to the memory device, the execution unit to execute one or more of the executable instructions. In some examples, the producer includes multiple portions such as application code, graphics pipeline runtime code, and command translation code segment.
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公开(公告)号：US11461959B2
公开(公告)日：2022-10-04
申请号：US16865587
申请日：2020-05-04
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
摘要： The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.
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公开(公告)号：US11252370B2
公开(公告)日：2022-02-15
申请号：US16939742
申请日：2020-07-27
申请人： Intel Corporation
发明人： Travis T. Schluessler , Joydeep Ray , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Karthik Vaidyanathan , Prasoonkumar Surti , Michael Apodaca , Murali Ramadoss , Abhishek Venkatesh
IPC分类号： H04N5/911
摘要： Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.
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公开(公告)号：US11132759B2
公开(公告)日：2021-09-28
申请号：US16237987
申请日：2019-01-02
申请人： Intel Corporation
发明人： Abhishek Venkatesh , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Prasoonkumar Surti
摘要： An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.
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公开(公告)号：US20210256653A1
公开(公告)日：2021-08-19
申请号：US17115555
申请日：2020-12-08
申请人： Intel Corporation
发明人： Saurabh Sharma , Michael Apodaca , Aditya Navale , Travis Schluessler , Vamsee Vardhan Chivukula , Abhishek Venkatesh , Subramaniam Maiyuran
IPC分类号： G06T1/20
摘要： An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.
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6.发明申请公开(公告)号：US20210097756A1
公开(公告)日：2021-04-01
申请号：US17018610
申请日：2020-09-11
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Joydeep Ray , Abhishek R. Appu
摘要： Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.
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公开(公告)号：US10861126B1
公开(公告)日：2020-12-08
申请号：US16449034
申请日：2019-06-21
申请人： Intel Corporation
发明人： Saurabh Sharma , Michael Apodaca , Aditya Navale , Travis Schluessler , Vamsee Vardhan Chivukula , Abhishek Venkatesh , Subramaniam Maiyuran
IPC分类号： G06T1/20
摘要： An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.
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公开(公告)号：US20200334896A1
公开(公告)日：2020-10-22
申请号：US16865587
申请日：2020-05-04
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
摘要： The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
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公开(公告)号：US10796397B2
公开(公告)日：2020-10-06
申请号：US14738679
申请日：2015-06-12
申请人： INTEL CORPORATION
发明人： James A. Valerio , Abhishek Venkatesh , Satyajit Sarangi , Michael Apodaca , Thomas F. Raoux , Hashem Hashemi , Rama S. B. Harihara
摘要： A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.
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公开(公告)号：US10748238B2
公开(公告)日：2020-08-18
申请号：US16279270
申请日：2019-02-19
申请人： Intel Corporation
发明人： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
摘要： A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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