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    MERGING ATOMICS TO THE SAME CACHE LINE
    1.
    发明公开
    MERGING ATOMICS TO THE SAME CACHE LINE 审中-公开

    公开(公告)号：US20240087077A1

    公开(公告)日：2024-03-14

    申请号：US17944542

    申请日：2022-09-14

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Prathamesh Raghunath Shinde ,  John Wiegert

    IPC: G06T1/60 ,  G06T1/20

    CPC classification number: G06T1/60 ,  G06T1/20

    Abstract: Embodiments described herein provide a technique to merge partial cache line writes to a cache memory. One embodiment provides a graphics processor comprising a graphics core, a cache coupled with the graphics core, and memory access circuitry to process memory access messages received from the graphics core. The memory access circuitry includes partial cache line write merge circuitry configured to merge a first partial write to a cache line of the cache with a second partial write to the cache line of the cache.

    64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE
    7.
    发明申请
    64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE 有权

    公开(公告)号：US20220413854A1

    公开(公告)日：2022-12-29

    申请号：US17358859

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Supratim Pal ,  Prathamesh Raghunath Shinde ,  Ben J. Ashbaugh ,  Changwon Rhee ,  Hong Jiang ,  FangWen Fu

    IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00

    Abstract: An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.

    PREFETCH AWARE LRU CACHE REPLACEMENT POLICY
    10.
    发明公开
    PREFETCH AWARE LRU CACHE REPLACEMENT POLICY 审中-公开

    公开(公告)号：US20240104025A1

    公开(公告)日：2024-03-28

    申请号：US17951914

    申请日：2022-09-23

    Applicant: Intel Corporation

    Inventor： Biju George ,  Zamshed I. Chowdhury ,  Prathamesh Raghunath Shinde ,  Chunhui Mei ,  Fangwen Fu

    IPC: G06F12/123 ,  G06F12/0862

    CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F2212/1021

    Abstract: Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.

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