公开(公告)号：US20220413854A1

公开(公告)日：2022-12-29

申请号：US17358859

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Supratim Pal ,  Prathamesh Raghunath Shinde ,  Ben J. Ashbaugh ,  Changwon Rhee ,  Hong Jiang ,  FangWen Fu

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.