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公开(公告)号：US12236498B2
公开(公告)日：2025-02-25
申请号：US17332596
申请日：2021-05-27
Applicant: Intel Corporation
Inventor： Saikat Mandal , Karol Szerszen , Vasanth Ranganathan , Altug Koker , Michael Norris , Prasoonkumar Surti , Takahiro Murata
Abstract: Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
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公开(公告)号：US20240354886A1
公开(公告)日：2024-10-24
申请号：US18599418
申请日：2024-03-08
Applicant: Intel Corporation
Inventor： Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Karol Szerszen , Prasoonkumar Surti
IPC: G06T1/20 , G06F9/38 , G06F16/907 , G06T7/90
CPC classification number: G06T1/20 , G06F9/3838 , G06F9/3877 , G06F16/907 , G06T7/90
Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.
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公开(公告)号：US20220383444A1
公开(公告)日：2022-12-01
申请号：US17332596
申请日：2021-05-27
Applicant: Intel Corporation
Inventor： Saikat Mandal , Karol Szerszen , Vasanth Ranganathan , Altug Koker , Michael Norris , Prasoonkumar Surti , Takahiro Murata
Abstract: Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
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公开(公告)号：US12223585B2
公开(公告)日：2025-02-11
申请号：US18376098
申请日：2023-10-03
Applicant: INTEL CORPORATION
Inventor： Karol Szerszen , Prasoonkumar Surti , Gabor Liktor , Karthik Vaidyanathan , Sven Woop
Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
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公开(公告)号：US11783530B2
公开(公告)日：2023-10-10
申请号：US17677109
申请日：2022-02-22
Applicant: INTEL CORPORATION
Inventor： Karol Szerszen , Prasoonkumar Surti , Gabor Liktor , Karthik Vaidyanathan , Sven Woop
CPC classification number: G06T15/06 , G06T1/20 , G06T15/005 , G06T15/08 , G06T17/10
Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
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Patent Agency Ranking
公开(公告)号：US10430990B2
公开(公告)日：2019-10-01
申请号：US15710828
申请日：2017-09-20
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge Garcia Pabon , Vasanth Ranganathan , Saikat Mandal , Karol Szerszen , Luis Cruz Camacho , Abhishek R. Appu , Joydeep Ray
Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
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公开(公告)号：US20250036608A1
公开(公告)日：2025-01-30
申请号：US18796619
申请日：2024-08-07
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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公开(公告)号：US11983791B2
公开(公告)日：2024-05-14
申请号：US17019479
申请日：2020-09-14
Applicant: Intel Corporation
Inventor： Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Karol Szerszen , Prasoonkumar Surti
IPC: G06T1/20 , G06F9/38 , G06F16/907 , G06T7/90
CPC classification number: G06T1/20 , G06F9/3838 , G06F9/3877 , G06F16/907 , G06T7/90
Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.
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公开(公告)号：US11556511B2
公开(公告)日：2023-01-17
申请号：US16371342
申请日：2019-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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公开(公告)号：US12086120B2
公开(公告)日：2024-09-10
申请号：US18066436
申请日：2022-12-15
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
CPC classification number: G06F16/2237 , G06N20/00 , G06T1/20
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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