公开(公告)号：US20190087999A1

公开(公告)日：2019-03-21

申请号：US15710828

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Garcia Pabon ,  Vasanth Ranganathan ,  Saikat Mandal ,  Karol Szerszen ,  Luis Cruz Camacho ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T15/00 ,  G06T15/40 ,  G09G5/00

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T9/00 ,  G06T15/40 ,  G09G5/006 ,  G09G2360/06 ,  H04N19/14

Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.

公开(公告)号：US10430990B2

公开(公告)日：2019-10-01

申请号：US15710828

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Garcia Pabon ,  Vasanth Ranganathan ,  Saikat Mandal ,  Karol Szerszen ,  Luis Cruz Camacho ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G09G5/00 ,  G06T9/00

Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.