公开(公告)号：US20240143333A1

公开(公告)日：2024-05-02

申请号：US18384714

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Liu Yang ,  Anbang YAO

IPC: G06F9/38 ,  G06F15/80 ,  G06N3/08 ,  G06N20/00

CPC classification number: G06F9/3867 ,  G06F9/3893 ,  G06F15/80 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20

Abstract: Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

公开(公告)号：US11868782B2

公开(公告)日：2024-01-09

申请号：US17887964

申请日：2022-08-15

Applicant: Intel Corporation

Inventor： Liu Yang ,  Anbang Yao

IPC: G06F9/30 ,  G06F9/38 ,  G06N20/00 ,  G06F15/80 ,  G06N3/08 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06F9/3867 ,  G06F9/3893 ,  G06F15/80 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06T15/005

Abstract: Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

公开(公告)号：US11551335B2

公开(公告)日：2023-01-10

申请号：US16474848

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Lin Xu ,  Liu Yang ,  Anbang Yao ,  Dongqi Cai ,  Libin Wang ,  Ping Hu ,  Shandong Wang ,  Wenhua Cheng ,  Yiwen Guo ,  Yurong Chen

IPC: G06T5/00 ,  G06N20/10 ,  G06F9/50 ,  G06N3/08 ,  G06N5/04 ,  H04N9/07 ,  H04N9/64

Abstract: Methods and systems are disclosed using camera devices for deep channel and Convolutional Neural Network (CNN) images and formats. In one example, image values are captured by a color sensor array in an image capturing device or camera. The image values provide color channel data. The captured image values by the color sensor array are input to a CNN having at least one CNN layer. The CNN provides CNN channel data for each layer. The color channel data and CNN channel data is to form a deep channel image that stored in a memory. In another example, image values are captured by sensor array. The captured image values by the sensor array are input a CNN having a first CNN layer. An output is generated at the first CNN layer using the captured image values by the color sensor array. The output of the first CNN layer is stored as a feature map of the captured image.

公开(公告)号：US11341368B2

公开(公告)日：2022-05-24

申请号：US16475079

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Anbang Yao ,  Shandong Wang ,  Wenhua Cheng ,  Dongqi Cai ,  Libin Wang ,  Lin Xu ,  Ping Hu ,  Yiwen Guo ,  Liu Yang ,  Yuqing Hou ,  Zhou Su ,  Yurong Chen

IPC: G06K9/62 ,  G06N3/08 ,  G06T1/20 ,  G06V10/94

Abstract: Methods and systems for advanced and augmented training of deep neural networks (DNNs) using synthetic data and innovative generative networks. A method includes training a DNN using synthetic data, training a plurality of DNNs using context data, associating features of the DNNs trained using context data with features of the DNN trained with synthetic data, and generating an augmented DNN using the associated features.

公开(公告)号：US10469868B2

公开(公告)日：2019-11-05

申请号：US14818886

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Yinglai Xi ,  Qiang Li ,  Jumei Li ,  Jianbin He ,  Jinfeng Zhou ,  Zhichong Chen ,  Liu Yang ,  Dong Li

IPC: H04N19/547 ,  H04N19/117 ,  H04N19/122 ,  H04N19/56 ,  H04N19/50 ,  H04N19/82 ,  H04N19/433 ,  H04N19/533 ,  H04N19/523

Abstract: An in-loop filtering acceleration circuit applied in a video codec system supporting the H.264 standard and the VC-1 standard is provided. The circuit includes multiple one-dimensional (1D) filters configured to perform a filtering process; and a filter selection unit configured to select one of the 1D filters according to the value of the boundary strength to perform the filtering processing to the reconstructed macroblock. The in-loop filtering acceleration circuit further divides the reconstructed macroblock into multiple 8×8 blocks and multiple 4×4 blocks, performs the filtering process to horizontal edges of the 8×8 blocks the reconstructed macroblock row by row from bottom to top, and performs the filtering process to horizontal edges of the 4×4 blocks row by row from top to bottom.

公开(公告)号：US09961354B2

公开(公告)日：2018-05-01

申请号：US15584572

申请日：2017-05-02

Applicant: INTEL CORPORATION

Inventor： Zhichong Chen ,  Jinfeng Zhou ,  Jianbin He ,  Liu Yang ,  Qiang Li

IPC: H04N19/433 ,  H04N19/51

CPC classification number: H04N19/433 ,  H04N19/51

Abstract: The invention provides a video codec. In one embodiment, the video codec is coupled to an outer memory storing a reference frame, and comprises an interface circuit, an in-chip memory, a motion estimation circuit, and a controller. The interface circuit obtains in-chip data from the reference frame stored in the outer memory. The in-chip memory stores the in-chip data. The motion estimation circuit retrieves search window data from the in-chip data with a search window, and performs a motion estimation process on a current macroblock according to the search-window data. The controller shifts the location of the search window when the current macroblock is shifted, marks a macroblock shifted out from the search window as an empty macroblock, and controls the interface circuit to obtain an updated macroblock for replacing the empty macroblock in the in-chip memory from the reference frame stored in the outer memory.

公开(公告)号：US20160284340A1

公开(公告)日：2016-09-29

申请号：US14369443

申请日：2013-12-12

Applicant: Honggng Li ,  Yuan Zhu ,  Bo Huang ,  Liu Yang ,  INTEL CORPORATION

Inventor： Honggang Li ,  Yuan Zhu ,  Bo Huang ,  Liu Yang

IPC: G10L13/033 ,  G10L13/10 ,  H04L29/06 ,  G06F3/16

CPC classification number: G10L13/033 ,  G06F3/165 ,  G09B21/006 ,  G10L13/10 ,  H04L63/10

Abstract: Systems and techniques of voice personalization for machine reading are described herein. A message with textual content may be received. A sender of the message may be identified. A voice model that corresponds to the sender may be identified. An audio representation of the textual content may be rendered using the voice model.

Abstract translation: 本文描述了用于机器读取的语音个性化的系统和技术。 可以接收具有文本内容的消息。 可以识别消息的发送者。 可以识别与发送者对应的语音模型。 可以使用语音模型来呈现文本内容的音频表示。

公开(公告)号：US09317768B2

公开(公告)日：2016-04-19

申请号：US13625962

申请日：2012-09-25

Applicant: Intel Corporation

Inventor： Qiang Li ,  Bin Wang ,  Liu Yang

IPC: G06K9/46

CPC classification number: G06K9/46

Abstract: Techniques for improved feature detection are described. In one embodiment, for example, a device may include a processor circuit and a feature detection module, and the feature detection module may be operative on the processor circuit to perform a first feature detection iteration for a graphics information element using an integral pixel value array, determine a scaling factor, recalculate the integral pixel value array based on the scaling factor, and perform a second feature detection iteration for the graphics information element using the recalculated integral pixel value array. Other embodiments are described and claimed.

Abstract translation: 描述了用于改进特征检测的技术。 在一个实施例中，例如，设备可以包括处理器电路和特征检测模块，并且特征检测模块可以在处理器电路上操作，以使用积分像素值阵列来执行图形信息元素的第一特征检测迭代 确定缩放因子，基于缩放因子重新计算积分像素值阵列，并且使用重新计算的积分像素值阵列对图形信息元素执行第二特征检测迭代。 描述和要求保护其他实施例。

公开(公告)号：US11461105B2

公开(公告)日：2022-10-04

申请号：US16475081

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Liu Yang ,  Anbang Yao

IPC: G06F9/30 ,  G06F9/38 ,  G06N20/00 ,  G06F15/80 ,  G06N3/08 ,  G06T1/20 ,  G06T15/00

Abstract: Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

公开(公告)号：US11080551B2

公开(公告)日：2021-08-03

申请号：US16607212

申请日：2017-05-22

Applicant: INTEL CORPORATION

Inventor： Liu Yang

IPC: G06K9/46 ,  G06T7/73 ,  G06K9/32 ,  G06K9/62

Abstract: An embodiment of a computer-implemented method generates a filtered set of region proposals for a digital image processing network. The method comprises generating a keypoint count map for a digital image, wherein the keypoint count map indicates how many keypoints have been detected near different pixels in the digital image. The method also comprises generating a keypoint integral image, wherein the keypoint integral image comprises a summed area table that is based on the keypoint count map. The method also comprises generating object existence indicators for an initial region set for the digital image based on the keypoint integral image, and extracting a keypoint-filtered region set from the initial region set based on the object existence indicators. The method may also comprise using the keypoint-filtered region set as region proposal input for an object proposal subsystem. Other embodiments are described and claimed.