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公开(公告)号：US12050540B2
公开(公告)日：2024-07-30
申请号：US18140808
申请日：2023-04-28
Applicant: NetApp, Inc.
Inventor： Abhijeet Gole , Ratnesh Gupta , Douglas Doucette
IPC: G06F12/10 , G06F12/1009
CPC classification number: G06F12/1009 , G06F2212/1021 , G06F2212/154 , G06F2212/214
Abstract: Methods, non-transitory machine-readable media, and computing devices that manage resources between multiple hosts coupled to dual-port solid-state disks (SSDs) are disclosed. With this technology, in-core conventional namespace (CNS) and zoned namespace (ZNS) mapping tables are synchronized by a host flash translation layer with on-disk CNS and ZNS mapping tables, respectively. An entry in one of the in-core CNS or ZNS mapping tables is identified based on whether a received storage operation is directed to a CNS or a ZNS of the dual-port SSD. The entry is further identified based on a logical address extracted from the storage operation. The storage operation is serviced using a translation in the identified entry for the logical address, when the storage operation is directed to the CNS, or a zone identifier in the identified entry for a zone of the ZNS, when the storage operation is directed to the ZNS.
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公开(公告)号：US12038844B2
公开(公告)日：2024-07-16
申请号：US18104180
申请日：2023-01-31
Applicant: Western Digital Technologies, Inc.
Inventor： Opher Lieber , Ariel Navon , Alexander Bazarsky , Shay Benisty
IPC: G06F12/0871 , G06F12/02 , G06F12/0893 , G06N20/00
CPC classification number: G06F12/0871 , G06F12/0246 , G06F12/0893 , G06N20/00 , G06F2212/214 , G06F2212/7205
Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.
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公开(公告)号：US20240193084A1
公开(公告)日：2024-06-13
申请号：US18504545
申请日：2023-11-08
Applicant: FLC Global, Ltd.
Inventor： Sehat Sutardja
IPC: G06F12/0811 , G06F3/06 , G06F9/4401 , G06F12/06 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G11C11/406
CPC classification number: G06F12/0811 , G06F3/061 , G06F3/0613 , G06F3/0638 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0683 , G06F9/4406 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G11C11/40607 , G06F12/0607 , G06F2212/1016 , G06F2212/1021 , G06F2212/152 , G06F2212/154 , G06F2212/161 , G06F2212/171 , G06F2212/20 , G06F2212/202 , G06F2212/214 , G06F2212/22 , G06F2212/222 , G06F2212/251 , G06F2212/305 , G06F2212/50 , G06F2212/60 , G06F2212/6022 , G06F2212/6032 , G06F2212/608 , G06F2212/62 , Y02D10/00
Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
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公开(公告)号：US11868257B2
公开(公告)日：2024-01-09
申请号：US17860263
申请日：2022-07-08
Applicant: Western Digital Technologies, Inc.
Inventor： Shay Benisty
IPC: G06F12/08 , G06F12/0815 , G06F12/0804 , G06F3/06 , G06F12/0868 , G06F12/0855 , G06F12/0871
CPC classification number: G06F12/0815 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0804 , G06F12/0855 , G06F12/0868 , G06F12/0871 , G06F2212/1024 , G06F2212/1032 , G06F2212/1056 , G06F2212/214 , G06F2212/312 , G06F2212/7203
Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.
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公开(公告)号：US11768610B2
公开(公告)日：2023-09-26
申请号：US17582746
申请日：2022-01-24
Applicant: KIOXIA CORPORATION
Inventor： Daisuke Hashimoto
CPC classification number: G06F3/0619 , G06F1/266 , G06F3/0604 , G06F3/064 , G06F3/067 , G06F3/0614 , G06F3/0625 , G06F3/0659 , G06F3/0665 , G06F3/0683 , G06F3/0688 , G06F11/1068 , G06F12/0246 , G11C5/144 , G11C5/147 , G11C5/148 , G11C29/52 , G06F2212/152 , G06F2212/214 , G06F2212/261 , G06F2212/263 , G06F2212/7201 , G06F2212/7211 , Y02D10/00
Abstract: A memory system includes an interface circuit configured to connect to a host device, a controller electrically connected to the interface circuit, and a nonvolatile semiconductor memory electrically connected to the controller. The controller is configured to transmit a first response in response to a power supplied from the host device via the interface circuit, upon receipt of a first command from the host device after transmitting the first response, determine a status of data stored in the nonvolatile semiconductor memory, and transmit to the host device a second response including the determined status of the data stored in the nonvolatile semiconductor memory.
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6.发明授权
公开(公告)号：US11740794B2
公开(公告)日：2023-08-29
申请号：US17527851
申请日：2021-11-16
Applicant: KIOXIA CORPORATION
Inventor： Masanobu Shirakawa , Tokumasa Hara
CPC classification number: G06F3/061 , G06F3/0634 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F12/0875 , G06F13/16 , G11C7/1063 , G11C16/10 , G11C16/26 , G06F2212/1016 , G06F2212/214 , G06F2212/452 , G06F2212/7203 , G06F2212/7207 , G11C7/24
Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
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7.发明公开
公开(公告)号：US20230267075A1
公开(公告)日：2023-08-24
申请号：US18310597
申请日：2023-05-02
Applicant: KIOXIA CORPORATION
Inventor： Kazuhiro FUKUTOMI , Kenichiro YOSHII , Shinichi KANNO , Shigehiro ASANO
CPC classification number: G06F12/0246 , G06F3/064 , G06F12/00 , G06F12/16 , G06F3/061 , G06F3/0631 , G06F3/0659 , G06F3/0679 , G06F3/0611 , G06F3/0688 , G06F2212/7205 , G06F3/0608 , G06F3/0644 , G06F3/0665 , G06F3/0638 , G06F2212/1016 , G06F2212/214 , G06F2212/7202
Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
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公开(公告)号：US20190179745A1
公开(公告)日：2019-06-13
申请号：US16255284
申请日：2019-01-23
Applicant: Toshiba Memory Corporation
Inventor： Kazuhiro Fukutomi , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
CPC classification number: G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F3/0688 , G06F12/00 , G06F12/16 , G06F2212/1016 , G06F2212/214 , G06F2212/7202 , G06F2212/7205
Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
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公开(公告)号：US20190096506A1
公开(公告)日：2019-03-28
申请号：US16148409
申请日：2018-10-01
Applicant: Seagate Technology LLC
Inventor： Timothy Canepa , Mark Ish , David S. Ebsen
CPC classification number: G11C29/789 , G06F12/0238 , G06F12/08 , G06F12/0868 , G06F2212/1016 , G06F2212/211 , G06F2212/214 , G06F2212/7203 , G11C7/1006 , G11C7/1084 , G11C7/18 , G11C8/14 , G11C11/005 , G11C2207/102 , G11C2207/2245 , G11C2207/2272
Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.
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10.发明申请
公开(公告)号：US20190034081A1
公开(公告)日：2019-01-31
申请号：US16147223
申请日：2018-09-28
Applicant: Toshiba Memory Corporation
Inventor： Masanobu SHIRAKAWA , Tokumasa Hara
CPC classification number: G06F3/061 , G06F3/0634 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F12/0875 , G06F13/16 , G06F2212/1016 , G06F2212/214 , G06F2212/452 , G06F2212/7203 , G06F2212/7207 , G11C7/1063 , G11C7/24 , G11C16/10 , G11C16/26
Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
