公开(公告)号：US11900113B2

公开(公告)日：2024-02-13

申请号：US17227590

申请日：2021-04-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lijuan Hai ,  Chen Cheng ,  Christopher Rodrigues ,  Peng Wu

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F8/30

CPC classification number: G06F9/3005 ,  G06F8/314 ,  G06F8/433 ,  G06F8/458 ,  G06F9/30087 ,  G06F9/3867 ,  G06F9/522

Abstract: The present disclosure relates to data flow processing methods and devices. One example method includes obtaining a dependency relationship and an execution sequence of operating a data flow by a plurality of processing units, generating synchronization logic based on the dependency relationship and the execution sequence, and inserting the synchronization logic into an operation pipeline of each of the plurality of processing unit to generate executable code.

公开(公告)号：US11755351B2

公开(公告)日：2023-09-12

申请号：US17834256

申请日：2022-06-07

Applicant: Google LLC

Inventor： Craig D. Chambers ,  Ashish Raniwala ,  Frances J. Perry ,  Stephen R. Adams ,  Robert R. Henry ,  Robert Bradshaw ,  Nathan Weizenbaum

IPC: G06F9/38 ,  G06F16/2453 ,  G06F21/57 ,  G06F9/445 ,  G06F9/455 ,  G06F21/62 ,  G06F8/41 ,  G06F9/48 ,  G06F8/30 ,  G06F8/34 ,  G06F9/44 ,  G06F9/448 ,  G06F9/30

CPC classification number: G06F9/45504 ,  G06F8/314 ,  G06F8/34 ,  G06F8/433 ,  G06F9/38 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/44 ,  G06F9/445 ,  G06F9/45533 ,  G06F9/4843 ,  G06F21/577 ,  G06F21/62 ,  G06F21/6218 ,  G06F9/30 ,  G06F9/4494 ,  G06F16/24532 ,  G06F16/24547 ,  G06F2221/034

Abstract: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.

公开(公告)号：US09934010B1

公开(公告)日：2018-04-03

申请号：US14675935

申请日：2015-04-01

Applicant: Mellanox Technologies Ltd.

Inventor： Patrick Robert Griffin ,  Walter Lee ,  Anant Agarwal ,  David M. Wentzlaff

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/445 ,  G06F8/30 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/437 ,  G06F8/447 ,  G06F8/451 ,  G06F8/453 ,  G06F9/48 ,  G06F9/546 ,  G06F2209/548

Abstract: Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

公开(公告)号：US09898348B2

公开(公告)日：2018-02-20

申请号：US14520505

申请日：2014-10-22

Applicant: International Business Machines Corporation

Inventor： Khary J. Alexander ,  Markus Helms ,  Christian Jacobi ,  Bernd Nerz ,  Volker Urban

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/00 ,  G06F9/52 ,  G06F9/44 ,  G06F9/45

CPC classification number: G06F9/52 ,  G06F8/10 ,  G06F8/314 ,  G06F8/45 ,  G06F9/5077

Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

公开(公告)号：US20180046440A1

公开(公告)日：2018-02-15

申请号：US15555643

申请日：2016-03-03

Applicant: Ingo Josopait

Inventor： Ingo Josopait

IPC: G06F9/45

CPC classification number: G06F8/423 ,  G06F8/314 ,  G06F8/433 ,  G06F8/434 ,  G06F9/4494

Abstract: The present invention discloses a method of flow control in a computing device, for processing of flow control statements to adapt a data structure of a program running on the computing device and a computer program product storing the method. The invention thereby allows the integration of the kernels into the main program when compiling. The whole parsing of the CPU program parts and the kernels is done by 10 one single standard compiler. The actual compiler for the device can be linked as a library and does not need to do any parsing. The invention further allows loops and if-clauses to be used in language-embedded GPGPU programming, enabling full general-purpose programming of the device in a way that is fully embedded in an ordinary programming language. The device can be a highly parallel computing 15 device, such as a video card, or some other computing device.

公开(公告)号：US09870257B1

公开(公告)日：2018-01-16

申请号：US14536447

申请日：2014-11-07

Applicant: VCE Company, LLC

Inventor： Changbin Gong ,  Srinivas Mantrala

IPC: G06F9/45 ,  G06F9/48 ,  G06F9/445 ,  G06F9/44

CPC classification number: G06F9/4881 ,  G06F8/314 ,  G06F8/45 ,  G06F8/71 ,  G06F9/44505 ,  G06F9/45512 ,  G06F9/45533

Abstract: A method of automation optimization in a command line interface is provided. The method includes receiving a configuration input that includes one or more commands and parsing the configuration input. The method also includes generating a command list that includes one or more tasks, based on the configuration input and populating a queue with the one or more tasks. The method includes executing each of the one or more tasks from the queue, on a command line interface and outputting a result, based on the executing.

公开(公告)号：US09864582B2

公开(公告)日：2018-01-09

申请号：US14675674

申请日：2015-03-31

Applicant: CAVIUM, INC.

Inventor： Kishore Badari Atreya ,  Ajeer Salil Pudiyapura ,  Ravindran Suresh

IPC: G06F9/44 ,  G06F9/45 ,  G06F15/78 ,  G06F9/30 ,  G06F15/76

CPC classification number: G06F8/33 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/445 ,  G06F8/447 ,  G06F8/451 ,  G06F8/70 ,  G06F9/30145 ,  G06F15/76 ,  G06F15/7825

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

公开(公告)号：US09836283B2

公开(公告)日：2017-12-05

申请号：US14675710

申请日：2015-03-31

Applicant: CAVIUM, INC.

Inventor： Ajeer Salil Pudiyapura ,  Kishore Badari Atreya ,  Ravindran Suresh

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/30 ,  G06F15/76 ,  G06F15/78

CPC classification number: G06F8/33 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/445 ,  G06F8/447 ,  G06F8/451 ,  G06F8/70 ,  G06F9/30145 ,  G06F15/76 ,  G06F15/7825

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

公开(公告)号：US09830157B2

公开(公告)日：2017-11-28

申请号：US12858907

申请日：2010-08-18

Applicant: Gagan Gupta ,  Gurindar S. Sohi ,  Srinath Sridharan

Inventor： Gagan Gupta ,  Gurindar S. Sohi ,  Srinath Sridharan

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/3838 ,  G06F8/314 ,  G06F8/456 ,  G06F8/458 ,  G06F9/4881 ,  G06F9/5033 ,  G06F9/5038

Abstract: A system and method of parallelizing programs employs runtime instructions to identify data accessed by program portions and to assign those program portions to particular processors based on potential overlap between the access data. Data dependence between different program portions may be identified and used to look for pending “predicate” program portions that could create data dependencies and to postpone program portions that may be dependent while permitting parallel execution of other program portions.

公开(公告)号：US20170228218A1

公开(公告)日：2017-08-10

申请号：US15017360

申请日：2016-02-05

Applicant: EMILIO SANTOS

Inventor： EMILIO SANTOS

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/24 ,  G06F8/314 ,  G06F8/41 ,  G06F8/45

Abstract: A system and method for creating a concurrent programming language by extending existing programming languages. The system and method may be useful for extending known concurrent programming languages, such as Java and C#. The system and method provides a compilation process that aids concurrent programming that aids concurrent programming by extending existing programming languages. The extended languages will support signals, concurrent objects, and concurrent expressions. The system and method does not use contracts or futures, but rather uses a different type of object that is understood with a different type of concurrent expression. In one embodiment, an asynchronous object is used.