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1.发明申请公开(公告)号：US20130116005A1
公开(公告)日：2013-05-09
申请号：US13464070
申请日：2012-05-04
Applicant: Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
Inventor： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
IPC: H04W88/06
CPC classification number: H04W88/06 , H04B1/0053 , H04B1/0458 , H04B1/0483 , H04B1/406
Abstract: A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.
Abstract translation: 多标准收发器包括公共平衡 - 不平衡变压器，控制器，至少一个第一开关和至少一个第二开关。 普通的不平衡变压器包括初级线圈和次级线圈。 所述至少一个第一开关响应于由控制器提供的控制信号将平衡 - 不平衡变换器的初级线圈连接到与第一通信标准相关联的第一信号路径或者与第二通信标准相关联的第二信号路径。 响应于由控制器提供的控制信号，至少一个第二开关将平衡 - 不平衡变换器的次级线圈连接到与第一通信标准相关联的第一放大路径，或者连接到与第二通信标准相关联的第二放大路径。 公共混频器被配置为根据选择了哪个通信标准来向一个信号路径提供上变频信号。
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2.发明申请System and Method for Controlling Excessive Parallelism in Multiprocessor Systems 有权用于控制多处理器系统中过多并行的系统和方法公开(公告)号：US20120180062A1
公开(公告)日：2012-07-12
申请号：US13005333
申请日：2011-01-12
Applicant: Gurindar S. Sohi , Srinath Sridharan , Gagan Gupta
Inventor： Gurindar S. Sohi , Srinath Sridharan , Gagan Gupta
IPC: G06F9/46
CPC classification number: G06F9/5066 , G06F2209/508 , Y02D10/22 , Y02D10/36
Abstract: Execution of a computer program on a multiprocessor system is monitored to detect possible excess parallelism causing resource contention and the like and, in response, to controllably limit the number of processors applied to parallelize program components.
Abstract translation: 监视多处理器系统上的计算机程序的执行以检测可能的过多的并行性导致资源争用等，并且作为响应可控制地限制应用于并行化程序组件的处理器的数量。
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公开(公告)号：US20070072558A1
公开(公告)日：2007-03-29
申请号：US11394249
申请日：2006-03-30
Applicant: Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
Inventor： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
CPC classification number: H04B1/0475
Abstract: A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.
Abstract translation: 一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。 使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。
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4.发明授权公开(公告)号：US08892159B2
公开(公告)日：2014-11-18
申请号：US13464070
申请日：2012-05-04
Applicant: Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
Inventor： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
CPC classification number: H04W88/06 , H04B1/0053 , H04B1/0458 , H04B1/0483 , H04B1/406
Abstract: A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.
Abstract translation: 多标准收发器包括公共平衡 - 不平衡变压器，控制器，至少一个第一开关和至少一个第二开关。 普通的不平衡变压器包括初级线圈和次级线圈。 所述至少一个第一开关响应于由控制器提供的控制信号将平衡 - 不平衡变换器的初级线圈连接到与第一通信标准相关联的第一信号路径或者与第二通信标准相关联的第二信号路径。 响应于由控制器提供的控制信号，至少一个第二开关将平衡 - 不平衡变换器的次级线圈连接到与第一通信标准相关联的第一放大路径，或者连接到与第二通信标准相关联的第二放大路径。 公共混频器被配置为根据选择了哪个通信标准来向一个信号路径提供上变频信号。
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公开(公告)号：US08787588B2
公开(公告)日：2014-07-22
申请号：US12713083
申请日：2010-02-25
Applicant: Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
Inventor： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
Abstract: Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.
Abstract translation: 本文公开了用于将扬声器耦合到集成电路的低引脚架构的系统和方法。 在一个实现中，低引脚架构有助于减少所需的引脚接口以将低功率扬声器，大功率扬声器和具有集成电路（IC）的耳机扬声器耦合。 为此，大功率扬声器可以在耦合到低功率扬声器的引脚接口和耳机扬声器之间交叉耦合。 这些引脚接口由相应的驱动电路驱动。 在所述实现中，可以共享一些驱动器电路以驱动多个引脚接口。 这些共享驱动器电路包括组合共源共栅电路，其具有与第二共源共栅电路集成的第一共源共栅电路，以可靠且选择性地驱动一个或多个引脚接口。
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Patent Agency Ranking
公开(公告)号：US20100220875A1
公开(公告)日：2010-09-02
申请号：US12713078
申请日：2010-02-25
Applicant: Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Lionel Cimaz
Inventor： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Lionel Cimaz
IPC: H02B1/00
CPC classification number: H04R3/002 , G10K11/002 , H04R3/00 , H04R3/007
Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.
Abstract translation: 公开了用于抑制音频信号中的弹出噪声的系统和方法。 该系统包括由引脚接口和互补引脚接口共享的驱动器电路。 控制单元耦合到引脚接口和互补引脚接口。 要激活引脚接口，控制单元配置为首先在互补引脚接口处激活驱动器输出。 一旦互补引脚接口达到预设电压，驱动器输出就由控制单元切换到引脚接口。 此外，可以通过重新使用在引脚接口处计算的校准数据，在互补引脚接口上校准驱动器电路的直流偏移。 此外，可以基于驱动器电路的校准数据从预偏置电路提供直流校正信号。
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7.发明授权Wireless communication device with self calibration feature for controlling power output 有权具有自校准功能的无线通信设备，用于控制功率输出公开(公告)号：US07609781B2
公开(公告)日：2009-10-27
申请号：US11427800
申请日：2006-06-30
Applicant: Donald A. Kerth , Srinath Sridharan
Inventor： Donald A. Kerth , Srinath Sridharan
Abstract: A wireless communication device is disclosed which employs a minimal number of power calibrations to set the output power of the device to a specified output power level. In one embodiment, the disclosed communication device includes a self calibrating feature that sets the output power level during initialization of the device.
Abstract translation: 公开了一种无线通信设备，其采用最小数量的功率校准来将设备的输出功率设置为指定的输出功率电平。 在一个实施例中，所公开的通信设备包括在设备的初始化期间设置输出功率电平的自校准特征。
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公开(公告)号：US09830157B2
公开(公告)日：2017-11-28
申请号：US12858907
申请日：2010-08-18
Applicant: Gagan Gupta , Gurindar S. Sohi , Srinath Sridharan
Inventor： Gagan Gupta , Gurindar S. Sohi , Srinath Sridharan
CPC classification number: G06F9/3838 , G06F8/314 , G06F8/456 , G06F8/458 , G06F9/4881 , G06F9/5033 , G06F9/5038
Abstract: A system and method of parallelizing programs employs runtime instructions to identify data accessed by program portions and to assign those program portions to particular processors based on potential overlap between the access data. Data dependence between different program portions may be identified and used to look for pending “predicate” program portions that could create data dependencies and to postpone program portions that may be dependent while permitting parallel execution of other program portions.
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9.发明授权System and method for controlling excessive parallelism in multiprocessor systems 有权用于控制多处理器系统中过度并行的系统和方法公开(公告)号：US08843932B2
公开(公告)日：2014-09-23
申请号：US13005333
申请日：2011-01-12
Applicant: Gurindar S. Sohi , Srinath Sridharan , Gagan Gupta
Inventor： Gurindar S. Sohi , Srinath Sridharan , Gagan Gupta
CPC classification number: G06F9/5066 , G06F2209/508 , Y02D10/22 , Y02D10/36
Abstract: Execution of a computer program on a multiprocessor system is monitored to detect possible excess parallelism causing resource contention and the like and, in response, to controllably limit the number of processors applied to parallelize program components.
Abstract translation: 监视多处理器系统上的计算机程序的执行以检测可能的过多的并行性导致资源争用等，并且作为响应可控制地限制应用于并行化程序组件的处理器的数量。
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10.发明申请System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens 有权使用数据关联令牌提供计算机软件的运行时并行化的系统和方法公开(公告)号：US20120066690A1
公开(公告)日：2012-03-15
申请号：US12882892
申请日：2010-09-15
Applicant: Gagan Gupta , Gurindar S. Sohi , Srinath Sridharan
Inventor： Gagan Gupta , Gurindar S. Sohi , Srinath Sridharan
IPC: G06F9/46
Abstract: A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens.
Abstract translation: 并行化程序的系统和方法将写入令牌和读取令牌分配给通过计算操作访问的数据对象。 在运行时间期间，用于计算操作的写入集合和读取集合被解析，并且只有在已经获得与分辨的写入和读取集合对应的数据对象的必要的令牌之后才执行计算操作。 数据对象可以具有无限制的读取令牌，但是只有单个写入令牌，并且只有在没有读取令牌未完成时才可以释放写入令牌。 数据对象提供等待列表，作为等待令牌的计算操作的有序队列。
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