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1.发明申请公开(公告)号：US20080074190A1
公开(公告)日：2008-03-27
申请号：US11900917
申请日：2007-09-12
Applicant: Pratap Singh , Chandrajit Debnath , Rakesh Malik , Arnold D'Souza
Inventor： Pratap Singh , Chandrajit Debnath , Rakesh Malik , Arnold D'Souza
CPC classification number: H03F3/45188 , H03F3/45677 , H03F2203/45052 , H03F2203/45074 , H03F2203/45248 , H03F2203/45296 , H03F2203/45302 , H03F2203/45318 , H03F2203/45342 , H03F2203/45356
Abstract: Embodiments of the present invention disclose operational amplifiers which demonstrate good settling behavior with minimum over-shoot or ringing for improving settling behavior. The amplifiers include one or more amplification stages connected to form a symmetric structure. The amplification stage includes a boosting amplifier, a MOS transistor and a compensation capacitor. The MOS transistor can be an NMOS transistor and a PMOS transistor. Using this scheme pole-zero doublets are rearranged in a manner to improve the transient settling response.
Abstract translation: 本发明的实施例公开了运行放大器，其以最小的过冲或振铃来表现出良好的沉降行为，以改善沉降行为。 放大器包括一个或多个连接以形成对称结构的放大级。 放大级包括升压放大器，MOS晶体管和补偿电容器。 MOS晶体管可以是NMOS晶体管和PMOS晶体管。 使用该方案，极点双重重排以改善瞬态稳定响应的方式。
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公开(公告)号：US08787588B2
公开(公告)日：2014-07-22
申请号：US12713083
申请日：2010-02-25
Applicant: Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
Inventor： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
Abstract: Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.
Abstract translation: 本文公开了用于将扬声器耦合到集成电路的低引脚架构的系统和方法。 在一个实现中，低引脚架构有助于减少所需的引脚接口以将低功率扬声器，大功率扬声器和具有集成电路（IC）的耳机扬声器耦合。 为此，大功率扬声器可以在耦合到低功率扬声器的引脚接口和耳机扬声器之间交叉耦合。 这些引脚接口由相应的驱动电路驱动。 在所述实现中，可以共享一些驱动器电路以驱动多个引脚接口。 这些共享驱动器电路包括组合共源共栅电路，其具有与第二共源共栅电路集成的第一共源共栅电路，以可靠且选择性地驱动一个或多个引脚接口。
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公开(公告)号：US20100220868A1
公开(公告)日：2010-09-02
申请号：US12713083
申请日：2010-02-25
Applicant: Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
Inventor： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
Abstract: Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.
Abstract translation: 本文公开了用于将扬声器耦合到集成电路的低引脚架构的系统和方法。 在一个实现中，低引脚架构有助于减少所需的引脚接口以将低功率扬声器，大功率扬声器和具有集成电路（IC）的耳机扬声器耦合。 为此，大功率扬声器可以在耦合到低功率扬声器的引脚接口和耳机扬声器之间交叉耦合。 这些引脚接口由相应的驱动电路驱动。 在所述实现中，可以共享一些驱动器电路以驱动多个引脚接口。 这些共享驱动器电路包括组合共源共栅电路，其具有与第二共源共栅电路集成的第一共源共栅电路，以可靠且选择性地驱动一个或多个引脚接口。
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