知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.026 seconds)

    Digital variable gain mixer
    3.
    发明申请
    Digital variable gain mixer 有权
    数字可变增益混频器

    公开(公告)号：US20070072558A1

    公开(公告)日：2007-03-29

    申请号：US11394249

    申请日：2006-03-30

    Applicant: Srinath Sridharan ,  Ahmed Emira ,  Aria Eshraghi ,  David Welland

    Inventor： Srinath Sridharan ,  Ahmed Emira ,  Aria Eshraghi ,  David Welland

    IPC: H01Q11/12 ,  H04B1/04

    CPC classification number: H04B1/0475

    Abstract: A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.

    Abstract translation: 一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。 使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。

    Direct digital access arrangement circuitry and method for connecting to phone lines
    4.
    发明申请
    Direct digital access arrangement circuitry and method for connecting to phone lines 失效

    公开(公告)号：US20060215771A1

    公开(公告)日：2006-09-28

    申请号：US11398090

    申请日：2006-04-05

    Applicant: Jeffrey Scott ,  Navdeep Sooch ,  David Welland

    Inventor： Jeffrey Scott ,  Navdeep Sooch ,  David Welland

    IPC: H04L25/00

    CPC classification number: H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

    System and method for determining capacitance value
    5.
    发明授权
    System and method for determining capacitance value 有权
    用于确定电容值的系统和方法

    公开(公告)号：US08193822B2

    公开(公告)日：2012-06-05

    申请号：US12494417

    申请日：2009-06-30

    Applicant: David Welland

    Inventor： David Welland

    IPC: G01R27/26

    CPC classification number: G01R27/2605 ,  H03K17/9622

    Abstract: A circuit for determining a value of a variable capacitor includes first circuitry for generating a first indication when a variable voltage across the variable capacitor exceeds a threshold voltage. Second circuitry generates a second indication when a reference voltage across a reference capacitor exceeds the threshold voltage. Control logic responsive to the first and second indications generate a control signal indicating whether the first indication or the second indication occurs first. A successive approximation engine generates an N-bit control value responsive to the control signal. A variable current source is responsive to the N-bit control value for generating a variable current to the first circuitry. A reference current source generates a reference current to the second circuitry.

    Abstract translation: 用于确定可变电容器的值的电路包括当可变电容器两端的可变电压超过阈值电压时产生第一指示的第一电路。 当参考电容两端的参考电压超过阈值电压时，第二电路产生第二指示。 响应于第一和第二指示的控制逻辑产生指示第一指示或第二指示是否首先出现的控制信号。 逐次逼近引擎响应于控制信号产生N位控制值。 可变电流源响应于N位控制值以产生到第一电路的可变电流。 参考电流源产生到第二电路的参考电流。

    LOW POWER MULTI-TOUCH SCAN CONTROL SYSTEM
    6.
    发明申请
    LOW POWER MULTI-TOUCH SCAN CONTROL SYSTEM 审中-公开
    低功耗多触控扫描控制系统

    公开(公告)号：US20120054379A1

    公开(公告)日：2012-03-01

    申请号：US12870849

    申请日：2010-08-30

    Applicant: Kafai Leung ,  Brent Wilson ,  Yonghong Tao ,  Shan Wang ,  Shantonu Bhadury ,  Suby Pellissery ,  Raghavendra Pai Kateel ,  David Welland ,  David Andreas ,  Gabriel Vogel

    Inventor： Kafai Leung ,  Brent Wilson ,  Yonghong Tao ,  Shan Wang ,  Shantonu Bhadury ,  Suby Pellissery ,  Raghavendra Pai Kateel ,  David Welland ,  David Andreas ,  Gabriel Vogel

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  G06F1/3206 ,  G06F1/3262 ,  G06F1/3275 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04104 ,  Y02D10/13 ,  Y02D10/14

    Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral. The DMA operates in a full power DMA mode when data transfer is required and a low power DMA mode when data transfer is not required. The central processing unit is operable, in the normal full system power mode, to interface with the memory and with the at least one peripheral unit to access data stored by the at least one peripheral unit.

    Abstract translation: 公开了一种集成控制电路，其包括以正常全系统功率模式和降低的系统低功率模式操作的中央处理单元和存储器。 提供多个外围单元，其中至少一个包括用于与至少外部系统进行接口以从其接收信息的输入/输出和处理块。 处理块处理来自外部系统的接收到的信息，并且在接收到的信息的处理期间，将数据存储在至少一个外围单元中，并且数据至少传送到或至少从存储器传送。 输入/输出和过程模块可以在全系统电源模式和降低的系统电源模式下完全工作。 直接存储器访问（DMA）在外围设备需要这种数据传输时，直接在至少一个外围设备和存储器之间传输数据。 当需要数据传输时，DMA工作在全功率DMA模式，而在不需要数据传输时，DMA工作在低功耗DMA模式。 中央处理单元在正常全系统功率模式下可操作地与存储器和至少一个外围单元接口以访问由至少一个外围单元存储的数据。

    Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications
    7.
    发明申请
    Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications 有权
    用于操作用于合成用于无线通信的高频信号的PLL的方法和装置

    公开(公告)号：US20050266817A1

    公开(公告)日：2005-12-01

    申请号：US11180267

    申请日：2005-07-13

    Applicant: David Welland ,  Caiyi Wang

    Inventor： David Welland ,  Caiyi Wang

    IPC: H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/193 ,  H03L7/199 ,  H03L7/23 ,  H04B1/06 ,  H04B1/40 ,  H04B7/00

    CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

    Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

    Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling an oscillator
    9.
    发明申请
    Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling an oscillator 有权
    用于产生对于控制振荡器特别有用的多个模拟控制信号的数字扩展器装置和方法

    公开(公告)号：US20050134491A1

    公开(公告)日：2005-06-23

    申请号：US10998521

    申请日：2004-11-29

    Applicant: Yunteng Huang ,  Bruno Garlepp ,  David Welland

    Inventor： Yunteng Huang ,  Bruno Garlepp ,  David Welland

    IPC: H03L7/00 ,  H03L7/099 ,  H03M1/00 ,  H03M1/66 ,  H03M3/00

    CPC classification number: H03L7/093 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06 ,  H03M7/3011 ,  H03M7/3028 ,  H03M7/3037

    Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

    Abstract translation: 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

    Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting
    10.
    发明申请
    Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting 失效
    用于连接到具有可编程限流的DC保持电路的电话线路的数字接入配置电路和方法

    公开(公告)号：US20050100104A1

    公开(公告)日：2005-05-12

    申请号：US10679013

    申请日：2003-10-03

    Applicant: Timothy Dupuis ,  George Tuttle ,  Jeffrey Scott ,  Navdeep Sooch ,  David Welland

    Inventor： Timothy Dupuis ,  George Tuttle ,  Jeffrey Scott ,  Navdeep Sooch ,  David Welland

    IPC: H04L7/033 ,  H04L25/06 ,  H04M11/06 ,  H04M19/00 ,  H04L25/00

    CPC classification number: H04L25/06 ,  H04L7/033 ,  H04L25/0266 ,  H04M11/06 ,  H04M19/001

    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

    Abstract translation: 可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。 简要描述，DAA提供用于各种国际电话标准的DC终端的可编程装置。 本发明还可以用于在电容隔离屏障上传输和接收信号的装置。 更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。 在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。 此外，大部分功率可能会在外部无源器件（如电阻）中消散。

Patent Agency Ranking