公开(公告)号：US20130329771A1

公开(公告)日：2013-12-12

申请号：US13492625

申请日：2012-06-08

Applicant: Lee M. Savage ,  James E. Henry ,  Jeffrey J. Becker ,  David Brent Wilson

Inventor： Lee M. Savage ,  James E. Henry ,  Jeffrey J. Becker ,  David Brent Wilson

IPC: H04B7/17

CPC classification number: G01S7/021 ,  G01S7/38

Abstract: A signal repeater (200) includes a signal processing part (202) and a signal repeating part (204). The signal processing part includes a converter (300) configured to receive an input signal and to convert the input signal into quadrature signals, and a processor (302, 304, 306) configured to process the quadrature signals to determine one or more characteristics of the input signal, and to compare the one or more characteristics of the input signal and a plurality of predetermined characteristics to generate a comparison result. The signal repeating part (204) is configured to selectively repeat the input signal as a repeated signal in accordance with the comparison result.

Abstract translation: 信号中继器（200）包括信号处理部分（202）和信号重复部分（204）。 信号处理部分包括被配置为接收输入信号并将输入信号转换为正交信号的转换器（300），以及配置成处理正交信号以确定一个或多个特征的处理器（302,304,306） 输入信号，并且比较输入信号的一个或多个特性和多个预定特性以产生比较结果。 信号重复部分（204）被配置为根据比较结果选择性地重复输入信号作为重复信号。

公开(公告)号：US20110062785A1

公开(公告)日：2011-03-17

申请号：US12570088

申请日：2009-09-30

Applicant: Michael Keith Odland ,  Brent Wilson

Inventor： Michael Keith Odland ,  Brent Wilson

IPC: H02J1/00

CPC classification number: H02J1/10 ,  H02J1/14 ,  Y10T307/505 ,  Y10T307/549 ,  Y10T307/653 ,  Y10T307/696

Abstract: A current limited system for providing a burst current capability comprises a variable load having a first mode of operation requiring a first current level and a burst current mode of operation requiring a second current level. The second current level is greater than the first current level. A control processor provides control signals for the current limited system. A voltage source is connected to the variable load to provide a source current. The source current provides the variable load the first current level in the first mode of operation. A burst mode circuit provides the second current level to the variable load in the burst current mode of operation, responsive to the control signals from the control processor and the voltage source.

Abstract translation: 用于提供突发电流能力的电流限制系统包括具有需要第一电流电平的第一操作模式和需要第二电流电平的突发电流操作模式的可变负载。 第二个当前级别大于第一个当前级别。 控制处理器为当前受限系统提供控制信号。 电压源连接到可变负载以提供源极电流。 源电流在第一种工作模式下提供可变负载的第一电流电平。 突发模式电路响应于来自控制处理器和电压源的控制信号，在突发电流操作模式中向可变负载提供第二电流电平。

公开(公告)号：US20090322410A1

公开(公告)日：2009-12-31

申请号：US12146352

申请日：2008-06-25

Applicant: Thomas S. David ,  Brian Caloway ,  Golam Chowdhury ,  Brent Wilson ,  Farris Bar ,  Douglas Piasecki

Inventor： Thomas S. David ,  Brian Caloway ,  Golam Chowdhury ,  Brent Wilson ,  Farris Bar ,  Douglas Piasecki

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F3/0416

Abstract: A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes.

Abstract translation: 电容式触摸传感器电路包括用于与连接到电容式传感器阵列的行和列的多个I / O引脚互连的接口。 响应于来自多个I / O引脚的输入的监控电路确定电容式传感器阵列中的电容开关何时已被致动并且存储电容开关的致动指示。 监控电路然后响应所确定的致动产生中断。 控制引擎控制监视电路监视多个I / O引脚的方式。 控制引擎和监控电路可以被配置为以多种操作模式监视多个I / O引脚。

公开(公告)号：US07159047B2

公开(公告)日：2007-01-02

申请号：US10829646

申请日：2004-04-21

Applicant: Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Brent Wilson ,  Lee Hoyman ,  Bruce Tyda

Inventor： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Brent Wilson ,  Lee Hoyman ,  Bruce Tyda

IPC: G06F13/00

CPC classification number: H04L12/40

Abstract: A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

Abstract translation: 公开了具有互连网络和多个处理块的电路。 互连网络具有在第一基板上以二维阵列布置的多个网络节点。 每个网络节点具有多个通信端口，并且通过仅连接那些两个网络节点和与该通信总线相邻的处理块的通信总线连接到每个相邻的网络节点。 响应于存储在该节点中的存储器中的连接信息，每个节点内的可编程开关将一个输入端口连接到其中一个输出端口。 可以通过包括覆盖在第一衬底上的第二衬底并且包括通过一个或多个节点垂直连接的第二这样的互连网络来构造三维实施例。 该电路容易地容纳可以通过改变连接信息来代替有缺陷的块的备用处理块。

公开(公告)号：US20050270108A1

公开(公告)日：2005-12-08

申请号：US10865110

申请日：2004-06-10

Applicant: Brent Wilson ,  Paul Highley ,  Kenneth Fernald

Inventor： Brent Wilson ,  Paul Highley ,  Kenneth Fernald

IPC: H03B1/00 ,  H03L1/02 ,  H03L7/08

CPC classification number: H03L7/08 ,  H03L1/02

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract translation: 用于在基于处理器的系统中校准低频振荡器的方法和装置。 一种用于校准片上非精密振荡器的方法。 提供具有在可接受的工作公差内的已知操作频率的片上精密振荡器。 片上精密振荡器用作时基，然后根据时基测量片上振荡器的周期。 然后确定片上非精密振荡器的测量频率与片上非精密振荡器的期望工作频率之间的差异。 在确定差异之后，调整片上非精密振荡器的频率以使确定的差最小化。

公开(公告)号：US20130120656A1

公开(公告)日：2013-05-16

申请号：US13810734

申请日：2011-07-20

Applicant: Brent Wilson ,  Robin Atkins

Inventor： Brent Wilson ,  Robin Atkins

IPC: H04N5/445

CPC classification number: H04N21/25825 ,  G06F3/1423 ,  G06F3/1462 ,  G09G5/005 ,  G09G5/04 ,  G09G5/06 ,  G09G2320/0242 ,  G09G2320/0276 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G2320/0666 ,  G09G2320/08 ,  G09G2360/02 ,  G09G2360/04 ,  G09G2360/144 ,  G09G2370/022 ,  G09G2370/04 ,  H04N5/445 ,  H04N21/234336 ,  H04N21/23439 ,  H04N21/2353 ,  H04N21/23614 ,  H04N21/42202 ,  H04N21/4318 ,  H04N21/4348 ,  H04N21/6125 ,  H04N21/6336 ,  H04N21/6379 ,  H04N21/84

Abstract: A display management unit configured to provide a modified video signal for display on a target display over an electronic distribution network. The unit may access information regarding the target display and at least one input. The unit comprises a database interface configured to retrieve display characteristics corresponding to the information regarding the target display from a characteristics database, and a mapping unit configured to map at least one of tone and color values from the at least one input to corresponding mapped values based at least in part on the retrieved display characteristics to produce the modified video signal.

Abstract translation: 一种显示管理单元，被配置为提供经过电子分配网络在目标显示器上显示的修改的视频信号。 该单元可以访问关于目标显示和至少一个输入的信息。 该单元包括被配置为从特征数据库检索与关于目标显示的信息相对应的显示特征的数据库接口，以及映射单元，被配置为将来自至少一个输入的色调值和颜色值中的至少一个映射到相应的映射值 至少部分地基于所检索的显示特性以产生经修改的视频信号。

公开(公告)号：US20120054379A1

公开(公告)日：2012-03-01

申请号：US12870849

申请日：2010-08-30

Applicant: Kafai Leung ,  Brent Wilson ,  Yonghong Tao ,  Shan Wang ,  Shantonu Bhadury ,  Suby Pellissery ,  Raghavendra Pai Kateel ,  David Welland ,  David Andreas ,  Gabriel Vogel

Inventor： Kafai Leung ,  Brent Wilson ,  Yonghong Tao ,  Shan Wang ,  Shantonu Bhadury ,  Suby Pellissery ,  Raghavendra Pai Kateel ,  David Welland ,  David Andreas ,  Gabriel Vogel

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F1/3206 ,  G06F1/3262 ,  G06F1/3275 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04104 ,  Y02D10/13 ,  Y02D10/14

Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral. The DMA operates in a full power DMA mode when data transfer is required and a low power DMA mode when data transfer is not required. The central processing unit is operable, in the normal full system power mode, to interface with the memory and with the at least one peripheral unit to access data stored by the at least one peripheral unit.

Abstract translation: 公开了一种集成控制电路，其包括以正常全系统功率模式和降低的系统低功率模式操作的中央处理单元和存储器。 提供多个外围单元，其中至少一个包括用于与至少外部系统进行接口以从其接收信息的输入/输出和处理块。 处理块处理来自外部系统的接收到的信息，并且在接收到的信息的处理期间，将数据存储在至少一个外围单元中，并且数据至少传送到或至少从存储器传送。 输入/输出和过程模块可以在全系统电源模式和降低的系统电源模式下完全工作。 直接存储器访问（DMA）在外围设备需要这种数据传输时，直接在至少一个外围设备和存储器之间传输数据。 当需要数据传输时，DMA工作在全功率DMA模式，而在不需要数据传输时，DMA工作在低功耗DMA模式。 中央处理单元在正常全系统功率模式下可操作地与存储器和至少一个外围单元接口以访问由至少一个外围单元存储的数据。

公开(公告)号：US20120038782A1

公开(公告)日：2012-02-16

申请号：US13195300

申请日：2011-08-01

Applicant: Neil W. Messmer ,  Brent Wilson

Inventor： Neil W. Messmer ,  Brent Wilson

IPC: H04N7/00 ,  H04N5/225 ,  H04N11/06

CPC classification number: H04N19/467 ,  H04N21/84

Abstract: A system and method for enhancing data coherency and potential of at least one metadata associated with a video data configured to operate in a visual dynamic range (VDR) format is disclosed. The system comprises a metadata framing structure which includes a header start of frame bit set, a packet type bit set, a configuration bit set, a variable depth configuration/metadata bit set, a header end of frame bit set, a timestamp bit set for specifying a frame delay count to apply the at least one metadata to the video data and a checksum check bit set. The at least one metadata is designed to embed within a code word guard bit position of at least one color channel of the video data and adaptable to embed within the VDR pipeline to enhance the quality of the video data.

Abstract translation: 公开了一种用于增强数据一致性的系统和方法，以及与被配置为以视觉动态范围（VDR）格式操作的视频数据相关联的至少一个元数据的潜力。 该系统包括元数据成帧结构，其包括帧位集合的报头开始，分组类型位集合，配置位集合，可变深度配置/元数据位集合，帧位集合的报头结束，为 指定帧延迟计数以将至少一个元数据应用于视频数据和校验和校验位集合。 至少一个元数据被设计成嵌入在视频数据的至少一个颜色通道的代码字保护位位置中，并且可适应于嵌入在VDR流水线内以增强视频数据的质量。

公开(公告)号：US20090322711A1

公开(公告)日：2009-12-31

申请号：US12146349

申请日：2008-06-25

Applicant: THOMAS S. DAVID ,  BRIAN CALOWAY ,  GOLAM CHOWDHURY ,  BRENT WILSON ,  FARRIS BAR ,  DOUGLAS PIASECKI

Inventor： THOMAS S. DAVID ,  BRIAN CALOWAY ,  GOLAM CHOWDHURY ,  BRENT WILSON ,  FARRIS BAR ,  DOUGLAS PIASECKI

IPC: G06F3/01 ,  G09G5/00 ,  G09G3/36

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G09G3/18 ,  G09G2330/021 ,  G09G2360/144 ,  G09G2360/145

Abstract: An integrated circuit comprises a host interface control block for providing a connection between the integrated circuit and a master controller device. The integrated circuit further includes a plurality of I/O pins. A capacitive touch sense circuitry enables detection of actuation of at least one capacitor switch of a capacitive sensor array connected to at least a portion of the plurality of I/O pins. An LCD controller drives at least one LCD connected to at least a portion of the plurality of I/O pins. The integrated circuit, responsive to signals received from the master controller device over the host interface control block, may be configured to monitor outputs from the capacitive sensor array in a first mode of operation. In a second mode of operation, the capacitive sensor array may be configured to drive at least one LCD. Finally, in a third mode of operation, the integrated circuit may be configured to both monitor outputs of the capacitive sensor array and drive the at least one LCD.

Abstract translation: 集成电路包括用于提供集成电路和主控制器装置之间的连接的主机接口控制块。 集成电路还包括多个I / O引脚。 电容式触摸感测电路使得​​能够检测连接到多个I / O引脚的至少一部分的电容式传感器阵列的至少一个电容器开关的致动。 LCD控制器驱动连接到多个I / O引脚的至少一部分的至少一个LCD。 集成电路响应于通过主机接口控制块从主控制器设备接收到的信号，可被配置为在第一操作模式下监视来自电容式传感器阵列的输出。 在第二操作模式中，电容式传感器阵列可被配置成驱动至少一个LCD。 最后，在第三种操作模式中，集成电路可以被配置成既监视电容式传感器阵列的输出并驱动至少一个LCD。

公开(公告)号：US20090228485A1

公开(公告)日：2009-09-10

申请号：US12044033

申请日：2008-03-07

Applicant: Stephen Handy ,  Brent Wilson ,  Ramesh Arimilli ,  Corey Hulen

Inventor： Stephen Handy ,  Brent Wilson ,  Ramesh Arimilli ,  Corey Hulen

IPC: G06F7/08 ,  G06F17/30

CPC classification number: G06F17/30592 ,  G06F17/30557 ,  Y10S715/963

Abstract: Architecture for slicing data defined on both tabular data sources and in OLAP (online analytical processing) multidimensional data sources by time relative to the current date simultaneously with the same time intelligence (TI) filter on a dashboard page. The architecture employs a simple time period specification (STPS) language used to specify time periods in monitoring server TI filters, and key performance indicator (KPI) filters. The architecture maps all time dimensions to a common set of time aggregations (hierarchy) and to a common calendar.

Abstract translation: 用于在表格数据源和OLAP（在线分析处理）多维数据源中定义的数据的时间相对于当前日期与在仪表板页面上的同一时间智能（TI）过滤器进行切片的架构。 该架构采用简单的时间段规范（STPS）语言，用于指定监控服务器TI过滤器和关键性能指标（KPI）过滤器的时间段。 架构将所有时间维度映射到一组通用时间聚合（层次结构）和公用日历。