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公开(公告)号:US20240347499A1
公开(公告)日:2024-10-17
申请号:US18391942
申请日:2023-12-21
发明人: Hongjin Kim
IPC分类号: H01L23/00 , H01L25/065
CPC分类号: H01L24/49 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/06135 , H01L2224/45111 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45166 , H01L2224/45171 , H01L2224/4518 , H01L2224/45184 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/48227 , H01L2224/49109 , H01L2224/49112 , H01L2224/49113 , H01L2224/4917 , H01L2224/49175 , H01L2224/49177 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要: A semiconductor package includes a package substrate including a power pad and a ground pad that are spaced apart from each other in a first horizontal direction, first and second semiconductor chips on the package substrate, the first and second semiconductor chips being stacked in a stepped shape that extends in a second horizontal direction perpendicular to the first horizontal direction, and a plurality of connection wires that electrically connect the package substrate to the first semiconductor chip and/or the second semiconductor chip. The first semiconductor chip includes a plurality of lower option pads. The second semiconductor chip includes a plurality of upper option pads. The plurality of connection wires include a conductive wire that electrically connects at least one of first and second upper chip pads of the second semiconductor chip to at least one of the lower option pads of the first semiconductor chip.
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公开(公告)号:US20240347426A1
公开(公告)日:2024-10-17
申请号:US18753892
申请日:2024-06-25
申请人: ROHM CO., LTD.
发明人: Katsuhiro IWAI
IPC分类号: H01L23/495 , H01L23/00 , H01L23/31
CPC分类号: H01L23/49548 , H01L23/3107 , H01L23/3121 , H01L23/3142 , H01L23/4952 , H01L23/49541 , H01L23/49551 , H01L23/49582 , H01L23/562 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04026 , H01L2224/04042 , H01L2224/0603 , H01L2224/06181 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2224/49431 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/18301 , H01L2924/3512
摘要: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.
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公开(公告)号:US20240332259A1
公开(公告)日:2024-10-03
申请号:US18614959
申请日:2024-03-25
申请人: ROHM CO., LTD.
发明人: Keiji WADA
IPC分类号: H01L25/065 , H01L23/00 , H01L23/495 , H01L25/18 , H01L27/01
CPC分类号: H01L25/0657 , H01L23/49575 , H01L25/18 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/01 , H01L2224/06155 , H01L2224/06165 , H01L2224/29186 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48101 , H01L2224/48105 , H01L2224/48137 , H01L2224/48245 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2225/06531 , H01L2924/05042 , H01L2924/05442
摘要: An insulation chip includes first and second units bonded to each other. The first unit includes a first semiconductor substrate, a first element insulating layer including a first element front surface facing the second unit and a first element back surface, and first and fourth insulating elements buried in the first element insulating layer at positions spaced apart from the first element front surface. The second unit includes a second element insulating layer having a second element front surface and a second element back surface, and second and third insulating elements buried in the second element insulating layer at positions spaced apart from the second element front surface. When the second unit is bonded to the first unit, the first and second insulating elements are arranged to face each other, and the third and fourth insulating elements are arranged to face each other.
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公开(公告)号:US20240145413A1
公开(公告)日:2024-05-02
申请号:US18244443
申请日:2023-09-11
发明人: Makoto NISHIHARA
IPC分类号: H01L23/66 , H01L21/8252 , H01L23/00 , H01L23/495 , H01L25/16 , H01L27/06
CPC分类号: H01L23/66 , H01L21/8252 , H01L23/49589 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/165 , H01L27/0688 , H01L2223/6655 , H01L2224/05541 , H01L2224/05553 , H01L2224/05558 , H01L2224/05644 , H01L2224/0603 , H01L2224/06181 , H01L2224/32245 , H01L2224/32265 , H01L2224/3303 , H01L2224/33181 , H01L2224/45144 , H01L2224/48091 , H01L2224/48101 , H01L2224/48106 , H01L2224/4813 , H01L2224/48175 , H01L2224/48195 , H01L2224/48265 , H01L2224/49052 , H01L2224/49109 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2924/10253 , H01L2924/10254 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10336 , H01L2924/10337 , H01L2924/10344 , H01L2924/10346 , H01L2924/13064 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/30107
摘要: A semiconductor device includes a semiconductor chip including a substrate, a transistor provided on an upper surface of the substrate and having an input electrode to which a high frequency signal is input, an output electrode from which the high frequency signal is output, and a reference potential electrode to which a reference potential is supplied, and a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode, a first capacitor including a first lower electrode provided on the metal pattern and electrically connected to the metal pattern, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and a first bonding wire electrically connecting the first upper electrode and a first electrode which is any one of the input electrode and the output electrode.
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公开(公告)号:US11967543B2
公开(公告)日:2024-04-23
申请号:US18052456
申请日:2022-11-03
申请人: ROHM CO., LTD.
发明人: Toshio Hanada
IPC分类号: H01L23/482 , H01L21/50 , H01L21/56 , H01L23/373 , H01L23/498 , H01L23/538 , H01L25/07 , H01L25/11 , H01L25/18 , H02M7/00 , H01L23/00 , H01L23/31
CPC分类号: H01L23/482 , H01L21/50 , H01L21/565 , H01L23/3735 , H01L23/49811 , H01L23/49844 , H01L23/538 , H01L25/07 , H01L25/072 , H01L25/115 , H01L25/18 , H02M7/003 , H01L23/3107 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45015 , H01L2224/48227 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2224/92247 , H01L2924/00012 , H01L2924/00014 , H01L2924/10272 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/207 , H01L2924/30107 , H01L2924/30107 , H01L2924/00 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/92247 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/13055 , H01L2924/00 , H01L2924/1305 , H01L2924/00 , H01L2924/12032 , H01L2924/00 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2224/45099 , H01L2924/00014 , H01L2224/45015 , H01L2924/207
摘要: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.
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公开(公告)号:US11854937B2
公开(公告)日:2023-12-26
申请号:US17114020
申请日:2020-12-07
申请人: ROHM CO., LTD.
发明人: Katsuhiko Yoshihara , Masao Saito
IPC分类号: H01L23/473 , H02M7/00 , H05K7/20 , B60K11/02 , H01L25/18 , B60K1/00 , H01L23/495 , H01L23/498 , F28F3/02 , F28F3/04 , H01L23/10 , H01L25/07 , H01L23/367 , H02M7/5387 , H02M1/32 , B60K6/22 , H01L23/00 , H01L25/16 , H01L29/16 , H01L29/739 , H01L29/78
CPC分类号: H01L23/473 , B60K1/00 , B60K11/02 , F28F3/022 , F28F3/04 , H01L23/10 , H01L23/49541 , H01L23/49548 , H01L23/49551 , H01L23/49555 , H01L23/49838 , H01L25/072 , H01L25/18 , H02M7/003 , H05K7/209 , H05K7/2089 , H05K7/20927 , B60K6/22 , B60K2001/003 , B60Y2200/91 , B60Y2200/92 , F28F2230/00 , H01L23/3672 , H01L24/32 , H01L25/165 , H01L29/1608 , H01L29/7395 , H01L29/7802 , H01L29/7804 , H01L29/7813 , H01L2224/32245 , H01L2224/49113 , H01L2924/10272 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/14252 , H01L2924/19041 , H01L2924/19105 , H02M1/327 , H02M7/5387 , Y10S903/904
摘要: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.
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公开(公告)号:US11719725B2
公开(公告)日:2023-08-08
申请号:US17731978
申请日:2022-04-28
发明人: Tomaz Slivnik
CPC分类号: G01R15/205 , G01R15/20 , G01R19/00 , G01R21/00 , G01R21/006 , G01R21/08 , G01R22/06 , G01R33/07 , G01R33/09 , H01L2224/05554 , H01L2224/48195 , H01L2224/48247 , H01L2224/49113 , H01L2924/19105
摘要: In embodiments, it is provided an integrated device for providing a measure of a quantity dependent on current through an electrical conductor, having: a sensing and processing sub-system; an electrical conductor to conduct a current; an insulating material encapsulating the sensing and processing sub-system and maintaining the electrical conductor in a fixed and spaced relationship to the sensing and processing sub-system, wherein the insulating material is configured to insulate the electrical conductor from the sensing and processing sub-system; sensing circuitry comprising a plurality of magnetic field sensing elements arranged on the sensing and processing sub-system adjacent to the electrical conductor, wherein the sensing circuitry is configured to provide a measure of the quantity as a weighted sum and/or difference of outputs of the magnetic field sensing elements caused by the current flowing through the electrical conductor adjacent to the plurality of magnetic field sensing elements; a voltage sensing input for sensing a measure of voltage associated with the current conductor; and output circuitry on the sensing and processing sub-system arranged to provide an output measure of the quantity from the sensed measure of current and sensed measure of voltage.
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公开(公告)号:US11699641B2
公开(公告)日:2023-07-11
申请号:US17499018
申请日:2021-10-12
申请人: ROHM CO., LTD.
发明人: Hiroaki Matsubara , Yasumasa Kasuya
CPC分类号: H01L23/49575 , H01L21/48 , H01L21/56 , H01L23/4952 , H01L23/49503 , H01L23/49517 , H01L23/49531 , H01L23/49537 , H01L23/49548 , H01L23/645 , H01L24/06 , H01L24/45 , H01L24/49 , H01L24/85 , H01L23/3107 , H01L23/49582 , H01L24/05 , H01L24/48 , H01L24/78 , H01L2224/05014 , H01L2224/05554 , H01L2224/0612 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48471 , H01L2224/49109 , H01L2224/49113 , H01L2224/49171 , H01L2224/78301 , H01L2224/85205 , H01L2224/85439 , H01L2924/00012 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19042 , H01L2924/207 , H01L2924/00014 , H01L2224/45015 , H01L2924/207 , H01L2924/00014 , H01L2224/45099 , H01L2924/00014 , H01L2224/05599 , H01L2224/85439 , H01L2924/00014 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/48091 , H01L2224/85205 , H01L2924/00014 , H01L2224/78301 , H01L2924/00014 , H01L2224/48465 , H01L2224/48247 , H01L2924/00 , H01L2924/13055 , H01L2924/00 , H01L2924/13091 , H01L2924/00
摘要: A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.
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公开(公告)号:US11658100B2
公开(公告)日:2023-05-23
申请号:US17472362
申请日:2021-09-10
申请人: ROHM CO., LTD.
发明人: Katsuhiro Iwai
IPC分类号: H01L23/495 , H01L23/31 , H01L23/00
CPC分类号: H01L23/49548 , H01L23/3107 , H01L23/3121 , H01L23/3142 , H01L23/4952 , H01L23/49541 , H01L23/49551 , H01L23/49582 , H01L23/562 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04026 , H01L2224/04042 , H01L2224/0603 , H01L2224/06181 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2224/49431 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/18301 , H01L2924/3512 , H01L2924/181 , H01L2924/00012 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2924/00012 , H01L2924/00014 , H01L2224/45099 , H01L2224/48465 , H01L2224/48247 , H01L2924/00012 , H01L2924/00014 , H01L2224/05599 , H01L2924/00014 , H01L2224/29099 , H01L2224/48465 , H01L2224/48247 , H01L2924/00
摘要: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.
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公开(公告)号:US20190206827A1
公开(公告)日:2019-07-04
申请号:US15857888
申请日:2017-12-29
申请人: Intel Corporation
发明人: HANY ESKANDAR
IPC分类号: H01L23/00 , H01L23/31 , H01L23/498 , H01L25/10 , H01L21/56 , H01L25/065
CPC分类号: H01L24/49 , H01L21/565 , H01L23/3128 , H01L23/49816 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/17104 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48463 , H01L2224/49113 , H01L2924/14 , H01L2924/15311
摘要: A semiconductor package includes test pad stack disposed in a first region of an upper surface of a semiconductor package substrate. One or more semiconductor dies conductively couple to the test pad stack. A first end of a test wirebond conductively couples to the test pad stack. A dummy pad stack is disposed in a peripheral region on the upper surface of the semiconductor package substrate. A second end of the test wirebond conductively couples to the dummy pad stack. A mold compound disposed on, about, or across the first region and the peripheral regions of the upper surface of the semiconductor package substrate at least partially covering the semiconductor die stack. A first portion of the test wirebond is disposed in the cured mold compound. The peripheral regions may be trimmed from the semiconductor package substrate, exposing at least a second portion of the test wirebond.
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