公开(公告)号：US20190252282A1

公开(公告)日：2019-08-15

申请号：US16394803

申请日：2019-04-25

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Christian Hecht ,  Roland Rupp ,  Andre Kabakow

IPC: H01L23/31 ,  H01L29/808 ,  H01L29/78 ,  H01L29/70 ,  H01L29/66 ,  H01L29/47 ,  H01L27/06 ,  H01L23/29 ,  H01L21/56 ,  H01L21/308 ,  H01L21/283 ,  H01L21/28 ,  H01L21/02 ,  H01L29/872 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L23/3171 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28247 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/56 ,  H01L23/29 ,  H01L23/3192 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/1066 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66674 ,  H01L29/66901 ,  H01L29/70 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10346 ,  H01L2924/10373 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

公开(公告)号：US10014269B2

公开(公告)日：2018-07-03

申请号：US15654512

申请日：2017-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yueh-Chuan Lee ,  Chia-Chan Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/58 ,  H01L21/78 ,  H01L21/306 ,  H01L33/00

CPC classification number: H01L24/06 ,  H01L21/30604 ,  H01L21/78 ,  H01L23/585 ,  H01L24/03 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/05016 ,  H01L2224/06179 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/2064

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.

公开(公告)号：US20160190092A1

公开(公告)日：2016-06-30

申请号：US14909157

申请日：2013-09-13

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Markus WIMPLINGER

IPC: H01L23/00 ,  B81C3/00

CPC classification number: H01L24/83 ,  B81C3/001 ,  B81C2203/036 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32507 ,  H01L2224/8302 ,  H01L2224/83022 ,  H01L2224/8381 ,  H01L2224/83894 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01034 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01322 ,  H01L2924/10251 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10346 ,  H01L2924/1037 ,  H01L2924/10371 ,  H01L2924/10372 ,  H01L2924/10373 ,  H01L2924/10375 ,  H01L2924/10376 ,  H01L2924/10377 ,  H01L2924/10821 ,  H01L2924/10823 ,  H01L2924/10831 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0103

Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

Abstract translation: 一种通过以下方法将基底层和保护层构成的接合层施加于基板上的方法：将可氧化碱性材料作为基底层施加到基板的粘接侧，至少部分覆盖 具有至少部分可溶解在作为保护层的基础材料中的保护材料的基础层。 此外，本发明涉及相应的基板。

公开(公告)号：US09269655B2

公开(公告)日：2016-02-23

申请号：US14825382

申请日：2015-08-13

Applicant: International Rectifier Corporation

Inventor： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/495 ,  H01L25/00 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Abstract translation: 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US09217541B2

公开(公告)日：2015-12-22

申请号：US13894332

申请日：2013-05-14

Applicant: LuxVue Technology Corporation

Inventor： Stephen Bathurst ,  Hsin-Hua Hu ,  Andreas Bibl

IPC: H01L29/06 ,  F21K99/00 ,  H01L23/00 ,  H01L33/00

CPC classification number: F21K9/00 ,  B81C99/002 ,  H01L24/00 ,  H01L33/0095 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10336 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/10349 ,  H01L2924/10375 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  Y10T29/49002 ,  H01L2224/03 ,  H01L2924/00

Abstract: A stabilization structure includes a stabilization layer on a carrier substrate. The stabilization layer includes an array of staging cavities. An array of micro devices are within the array of staging cavities. Each micro device is laterally attached to a shear release post laterally extending from a sidewall of a staging cavity. A pressure is applied to the array of micro devices from the array of transfer heads to shear the array of micro devices off the shear release posts. The sheared off micro devices are picked up from the carrier substrate using the array of transfer heads.

Abstract translation: 稳定结构包括载体基底上的稳定层。 稳定层包括分段腔阵列。 微器件阵列在分级腔阵列内。 每个微器件横向地附接到从分级腔的侧壁横向延伸的剪切释放柱。 从转移头阵列向微器件阵列施加压力以将微器件阵列剪切离开剪切释放柱。 使用转移头阵列从载体衬底拾取剪切的微器件。

公开(公告)号：US08987883B2

公开(公告)日：2015-03-24

申请号：US14192756

申请日：2014-02-27

Applicant: International Rectifier Corporation

Inventor： Eung San Cho ,  Chuan Cheah

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract translation: 一个示例性的公开的实施例包括被配置为具有控制晶体管和设置在公共引线框焊盘上的同步晶体管的降压转换器的高功率半导体封装，用于驱动控制和同步晶体管的驱动器集成电路（IC） 晶体管的顶表面到衬底焊盘，例如引线框焊盘。 以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的接地或电流传导，从而与使用以下的传统封装方法相比，能够实现具有显着降低的电阻，形状因素，复杂性和成本的封装 用于晶体管互连的引线。

公开(公告)号：US20140340900A1

公开(公告)日：2014-11-20

申请号：US13894332

申请日：2013-05-14

Applicant: Luxvue Technology Corporation

Inventor： Stephen Bathurst ,  Hsin-Hua Hu ,  Andreas Bibl

IPC: H05K7/08 ,  F21K99/00

CPC classification number: F21K9/00 ,  B81C99/002 ,  H01L24/00 ,  H01L33/0095 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10336 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/10349 ,  H01L2924/10375 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  Y10T29/49002 ,  H01L2224/03 ,  H01L2924/00

Abstract: A stabilization structure includes a stabilization layer on a carrier substrate. The stabilization layer includes an array of staging cavities. An array of micro devices are within the array of staging cavities. Each micro device is laterally attached to a shear release post laterally extending from a sidewall of a staging cavity. A pressure is applied to the array of micro devices from the array of transfer heads to shear the array of micro devices off the shear release posts. The sheared off micro devices are picked up from the carrier substrate using the array of transfer heads.

Abstract translation: 稳定结构包括载体基底上的稳定层。 稳定层包括分段腔阵列。 微器件阵列在分级腔阵列内。 每个微器件横向地附接到从分级腔的侧壁横向延伸的剪切释放柱。 从转移头阵列向微器件阵列施加压力以将微器件阵列剪切离开剪切释放柱。 使用转移头阵列从载体衬底拾取剪切的微器件。

公开(公告)号：US20120168923A1

公开(公告)日：2012-07-05

申请号：US13095247

申请日：2011-04-27

Applicant: Eung San Cho ,  Chuan Cheah

Inventor： Eung San Cho ,  Chuan Cheah

IPC: H01L23/495

CPC classification number: H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract translation: 一个示例性的公开的实施例包括被配置为具有控制晶体管，同步晶体管，用于驱动控制和同步晶体管的驱动器集成电路（IC））的降压转换器的高功率半导体封装，以及从同步漏极 同步晶体管的顶表面到控制晶体管的顶表面上的控制源。 导电夹子还可以连接到衬底焊盘，例如用于电流输入和输出的引线框焊盘。 以这种方式，导电夹子通过直接机械连接和大的表面积导通来提供控制源和同步漏极之间的有效连接，从而与常规的相比，能够实现具有显着降低的电阻，形状因子，复杂性和成本的封装 封装方法使用引线用于晶体管互连。

公开(公告)号：US09627349B2

公开(公告)日：2017-04-18

申请号：US14909157

申请日：2013-09-13

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Markus Wimplinger

IPC: H01L23/00 ,  B81C3/00

CPC classification number: H01L24/83 ,  B81C3/001 ,  B81C2203/036 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32507 ,  H01L2224/8302 ,  H01L2224/83022 ,  H01L2224/8381 ,  H01L2224/83894 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01034 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01322 ,  H01L2924/10251 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10346 ,  H01L2924/1037 ,  H01L2924/10371 ,  H01L2924/10372 ,  H01L2924/10373 ,  H01L2924/10375 ,  H01L2924/10376 ,  H01L2924/10377 ,  H01L2924/10821 ,  H01L2924/10823 ,  H01L2924/10831 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0103

Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

公开(公告)号：US20160280918A1

公开(公告)日：2016-09-29

申请号：US15175833

申请日：2016-06-07

Applicant: MOMENTIVE PERFORMANCE MATERIALS JAPAN LLC

Inventor： Prakash KUMAR ,  Hideo TAKAHASHI

IPC: C08L83/04 ,  H01L33/56 ,  H01L23/00 ,  C09J183/04

CPC classification number: C08L83/04 ,  C08K3/36 ,  C08K5/098 ,  C08K5/3492 ,  C08L83/06 ,  C08L2203/206 ,  C08L2205/025 ,  C08L2205/05 ,  C09J183/04 ,  H01L23/296 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/56 ,  H01L33/62 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/45144 ,  H01L2224/48639 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2924/0715 ,  H01L2924/10346 ,  H01L2924/12041 ,  H01L2924/17747 ,  H01L2924/00012 ,  H01L2924/00014 ,  C08L83/00 ,  C08K5/56 ,  C08K5/34924

Abstract: There is provide an addition-curable silicone composition from which a silicone cured product having excellent adhesiveness and external appearance, being able to protect metal, in particular, silver, from corrosion, and having less shrinkage and change in hardness due to heat, is obtained. The addition-curable silicone composition contains: 100 parts by mass of a polyorganosiloxane having alkenyl groups; an amount of a polyorganohydrogensiloxane such that an amount of Si—H groups is 0.9 to 3.0 mol relative to 1 mol of the alkenyl groups; a catalyst amount of a hydrosilylation reaction catalyst; 0.01 to 10 parts of an adhesiveness imparting agent; and 0.001 to 0.015 parts by mass, in terms of metal atoms of (R3COO)kM (where M is Ce, Fe, Cr, La, Nd, Pr or Sm, k is 2, 3 or 4, and R3 represents a substituted or unsubstituted hydrocarbon group having 4 to 17 carbon atoms).

Abstract translation: 提供一种可加成固化的硅氧烷组合物，其具有优异的粘合性和外观的硅酮固化产物，其能够保护金属，特别是银，免受腐蚀，并且具有较小的收缩和由于热导致的硬度变化。 。 加成固化性有机硅组合物含有：100质量份具有烯基的聚有机硅氧烷; 一定量的聚有机氢硅氧烷，使得Si-H基团的量相对于1摩尔烯基为0.9-3.0摩尔; 催化剂量的氢化硅烷化反应催化剂; 0.01〜10份粘合性赋予剂; 和（R 3 COO）k M的金属原子（其中M为Ce，Fe，Cr，La，Nd，Pr或Sm，k为2,3或4）为0.001〜0.015质量份，R3表示取代或 未取代的碳原子数为4〜17的烃基）。