公开(公告)号：US09312209B2

公开(公告)日：2016-04-12

申请号：US14634510

申请日：2015-02-27

申请人： PS4 LUXCO S.A.R.L.

发明人： Kayoko Shibata ,  Hitoshi Miwa ,  Yoshihiko Inoue

IPC分类号： G06F9/455 ,  G06F17/50 ,  H01L23/48 ,  G11C5/06 ,  G11C29/02 ,  G11C29/12 ,  H01L25/065 ,  H01L27/108 ,  H01L23/538 ,  H01L27/105 ,  H01L21/66

CPC分类号： H01L27/10897 ,  G11C5/063 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0657 ,  H01L27/1052 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01055

摘要： A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n−x switch circuits to connect n−x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

摘要翻译： 一种用于通过硅穿过硅通孔中的x绕过缺陷的硅的方法，包括接收多个释放信号以通过x识别有缺陷的硅，激活x-1个开关电路以将x-1个数据电路连接到 通过硅通孔相邻的n组中的硅通孔1至x-1，激活n-x个开关电路以将n-x个数据电路连接到通过硅通孔相邻的n组中的硅通孔x + 1至n， 以及激活开关电路，以将数据电路连接到辅助硅通孔，所述辅助硅通过硅邻近通过硅通过硅通过硅通过硅通孔中的n组。

公开(公告)号：US09112001B2

公开(公告)日：2015-08-18

申请号：US14173406

申请日：2014-02-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Pao Shu ,  Chun-wen Cheng ,  Kuei-Sung Chang ,  Hsin-Ting Huang ,  Shang-Ying Tsai ,  Jung-Huei Peng

IPC分类号： H01L21/30 ,  H01L21/768 ,  B81C1/00 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/76838 ,  B81C1/00238 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05617 ,  H01L2224/05638 ,  H01L2224/061 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/26145 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29017 ,  H01L2224/2902 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29117 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29181 ,  H01L2224/301 ,  H01L2224/32058 ,  H01L2224/321 ,  H01L2224/32106 ,  H01L2224/32148 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83805 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/01037 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2924/0132 ,  H01L2924/00014

摘要： A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates.

摘要翻译： 形成封装系统的方法包括提供具有金属焊盘和至少一个金属保护环的第一基板。 该方法还包括用第二衬底的半导体焊盘接合第一衬底的金属焊盘，其中至少一个金属保护环被配置为至少部分地与半导体焊盘相互作用以形成至少第一部分的电 在第一和第二基板之间接合材料。

公开(公告)号：US09087571B2

公开(公告)日：2015-07-21

申请号：US14070266

申请日：2013-11-01

申请人： PS4 LUXCO S.A.R.L.

发明人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

IPC分类号： G11C7/00 ,  G11C7/22 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.

摘要翻译： 一种半导体器件，包括：接口芯片，包括：内部数据端子;以及定时数据存储电路，被配置为输出多个定时设置信号，以及多个芯片堆叠彼此堆叠，每个芯片芯片包括多个 存储单元，耦合到所述接口芯片的定时数据存储电路的输出控制电路，所述输出控制电路被配置为接收所述定时设置信号中的相应一个，并响应于所述存储单元中的相应一个输出定时信号 定时设定信号和耦合到接口芯片的内部数据端的数据输出电路，数据输出电路被配置为响应于输出定时信号输出数据，该数据从对应的一个存储单元导出。

公开(公告)号：US20150179549A1

公开(公告)日：2015-06-25

申请号：US14634510

申请日：2015-02-27

申请人： PS4 LUXCO S.A.R.L.

发明人： Kayoko Shibata ,  Hitoshi Miwa ,  Yoshihiko Inoue

IPC分类号： H01L23/48 ,  H01L27/105

CPC分类号： H01L27/10897 ,  G11C5/063 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0657 ,  H01L27/1052 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01055

摘要： A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n−x switch circuits to connect n−x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

摘要翻译： 一种用于通过硅穿过硅通孔中的x绕过缺陷的硅的方法，包括接收多个释放信号以通过x识别有缺陷的硅，激活x-1个开关电路以将x-1个数据电路连接到 通过硅通孔相邻的n组中的硅通孔1至x-1，激活n-x个开关电路以将n-x个数据电路连接到通过硅通孔相邻的n组中的硅通孔x + 1至n， 以及激活开关电路，以将数据电路连接到辅助硅通孔，所述辅助硅通过硅邻近通过硅通过硅通过硅通过硅通孔中的n组。

公开(公告)号：US08963301B1

公开(公告)日：2015-02-24

申请号：US14142457

申请日：2013-12-27

申请人： Amkor Technology, Inc.

发明人： Thomas P. Glenn

IPC分类号： H01L23/62 ,  H01L23/495

CPC分类号： H01L23/49503 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T428/24207 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Packages for an integrated circuit die and methods and lead frames for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wares, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.

摘要翻译： 公开了用于集成电路管芯的封装以及用于制造这种封装的方法和引线框架。 封装包括管芯，裸片焊盘，外围金属触点，粘合剂和密封剂。 管芯焊盘和触点位于封装的下表面。 管芯焊盘和触头具有侧表面，其包括凹入部分和粗糙度以接合密封剂。

公开(公告)号：US20140320203A1

公开(公告)日：2014-10-30

申请号：US14325436

申请日：2014-07-08

申请人： PS4 LUXCO S.A.R.L.

发明人： Kayoko Shibata ,  Hitoshi Miwa ,  Yoshihiko Inoue

IPC分类号： H01L27/105

CPC分类号： H01L27/10897 ,  G11C5/063 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0657 ,  H01L27/1052 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01055

摘要： A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

摘要翻译： 一种用于通过硅穿过硅通孔中的x绕过缺陷的硅的方法，包括接收多个释放信号以通过x识别有缺陷的硅，激活x-1个开关电路以将x-1个数据电路连接到 通过硅通孔相邻的n组中的硅通孔1至x-1，激活nx个开关电路，以将nx数据电路连接到通过硅通孔相邻的n组中的硅通孔x + 1至n，并激活开关 电路，用于将数据电路连接到通过硅穿过硅的辅助通孔，通过硅通过硅通过n通过硅通孔中的n个相邻。

公开(公告)号：US08839161B2

公开(公告)日：2014-09-16

申请号：US13872553

申请日：2013-04-29

申请人： Elpida Memory, Inc.

发明人： Kayoko Shibata ,  Hitoshi Miwa ,  Yoshihiko Inoue

IPC分类号： G06F17/50 ,  H01L27/108 ,  G11C29/12 ,  H01L23/538 ,  G11C29/02 ,  G11C5/06 ,  H01L25/065 ,  H01L23/48 ,  H01L21/66

CPC分类号： H01L27/10897 ,  G11C5/063 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0657 ,  H01L27/1052 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01055

摘要： A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias.

摘要翻译： 半导体器件包括包括多个驱动电路的第一半导体芯片和耦合到多个驱动电路的输出开关电路。 该器件还包括第二半导体芯片和设置在第一和第二半导体芯片中的至少一个上的多个通孔硅通孔。 输出开关电路耦合在多个驱动器电路和多个通孔硅通孔之间，并将来自多个驱动电路的每个信号输出到多个通孔硅通孔中的相应一个。

公开(公告)号：US08786085B2

公开(公告)日：2014-07-22

申请号：US13671573

申请日：2012-11-08

申请人： Infineon Technologies AG

发明人： Hans-Joachim Barth ,  Mathias Vaupel ,  Rainer Steiner ,  Werner Robl ,  Jens Pohl ,  Joern Plagmann ,  Gottfried Beer

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

摘要翻译： 一个或多个实施例涉及半导体结构，包括：覆盖工件表面的阻挡层; 覆盖阻挡层的种子层; 覆盖所述种子层的抑制剂层，所述抑制剂层具有暴露所述种子层的一部分的开口以及覆盖所述种子层的暴露部分的填充层。

公开(公告)号：US08735288B2

公开(公告)日：2014-05-27

申请号：US14082138

申请日：2013-11-16

申请人： Elpida Memory, Inc.

发明人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成第一和第二凸起，形成穿透半导体衬底的第一穿透电极和第二穿透电极，形成在第一凸起和第一穿透电极之间形成第一电路的第一导电结构，以及 形成在所述第二凸起和所述第二贯穿电极之间形成第二电路的第二导电结构，所述第二导电结构的电阻值比所述第一导电结构小。

公开(公告)号：US08710639B2

公开(公告)日：2014-04-29

申请号：US13639735

申请日：2011-02-22

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

IPC分类号： H01L23/02

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2924/00015 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2224/45 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/48

摘要： A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer. The adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of this second conductive part so as to surround the second conductive part.

摘要翻译： 构成半导体元件的布线基板包括半导体元件; 覆盖该半导体元件的至少外周侧表面的外围绝缘层; 以及设置在布线基板的上表面侧的上表面侧布线。 半导体元件包括电连接到半导体元件的上表面侧的上表面侧布线的内部端子。 该内部端子包括从半导体元件的绝缘表面层露出的第一导电部件; 在该第一导电部分上的粘附层; 和该粘合层上的第二导电部分。 粘合层覆盖第一导电部分的暴露表面，并且形成在第一导电部分的暴露表面周围的绝缘表面层的一部分上，并且粘合层围绕该第二导电部分的外边缘的外侧延伸 导电部件以包围第二导电部件。