公开(公告)号：US12094549B2

公开(公告)日：2024-09-17

申请号：US17889578

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Kitae Park

IPC: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3445 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

公开(公告)号：US20240292502A1

公开(公告)日：2024-08-29

申请号：US18659170

申请日：2024-05-09

Applicant: Lutron Technology Company LLC

Inventor： Russell Weightman ,  Jonathan T. Lenz ,  Jaykrishna A. Shukla ,  Daniel Curtis Raneri

IPC: H05B39/08 ,  G11C5/00 ,  G11C5/02 ,  G11C7/04 ,  G11C7/24 ,  G11C11/406 ,  G11C29/12 ,  H05B39/04 ,  H05B47/10 ,  H05B47/165 ,  H05B47/17 ,  H05B47/185

CPC classification number: H05B39/086 ,  G11C5/005 ,  G11C5/025 ,  G11C7/04 ,  G11C7/24 ,  G11C11/40626 ,  G11C29/12 ,  H05B39/04 ,  H05B47/10 ,  H05B47/165 ,  H05B47/17 ,  H05B47/185

Abstract: A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

公开(公告)号：US20240265987A1

公开(公告)日：2024-08-08

申请号：US18368086

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunseok KIM

IPC: G11C29/12 ,  G06F3/06

CPC classification number: G11C29/12 ,  G06F3/0614 ,  G06F3/0653 ,  G06F3/0673

Abstract: A memory repair circuit of a memory module including a plurality of memory packages, the memory repair circuit including: a test circuit configured to test the plurality of memory packages to obtain fail information in each of the plurality of memory packages; and a redundancy analysis circuit configured to: obtain a redundant address count in each of the plurality of memory packages, determine a repair order of the plurality of memory packages based on the fail information and the redundant address count, and perform a virtual repair on the plurality of memory packages in the repair order to determine an address to be repaired in each of the plurality of memory packages.

公开(公告)号：US20240194234A1

公开(公告)日：2024-06-13

申请号：US18443997

申请日：2024-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  H01L21/822

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US20240145020A1

公开(公告)日：2024-05-02

申请号：US18236751

申请日：2023-08-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHENG-LIN LIN ,  SHIH-CHIEH LIN

IPC: G11C29/12

CPC classification number: G11C29/12

Abstract: A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.

公开(公告)号：US11935624B2

公开(公告)日：2024-03-19

申请号：US18302560

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  H01L21/822

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US11928355B2

公开(公告)日：2024-03-12

申请号：US17647472

申请日：2022-01-10

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jian Chen ,  Chi-Shian Wu

IPC: G11C29/02 ,  G06F3/06 ,  G11C7/06 ,  G11C29/12

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/065 ,  G11C29/026 ,  G11C29/12

Abstract: Disclosed are a method and apparatus for determining mismatch of a sense amplifier, a storage medium, and an electronic equipment, relating to the field of integrated circuit technology. The method for determining mismatch of a sense amplifier includes: determining a first signal threshold on a first bit line when a first memory cell executes write and read operations; determining a second signal threshold on a second bit line when a second memory cell executes write and read operations; and determining, according to the first signal threshold and the second signal threshold, whether the sense amplifier is mismatched. A method for determining whether the sense amplifier is mismatched is provided.

公开(公告)号：US20240070069A1

公开(公告)日：2024-02-29

申请号：US18215474

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11868253B2

公开(公告)日：2024-01-09

申请号：US17861627

申请日：2022-07-11

Applicant: Lodestar Licensing Group, LLC

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G11C11/00 ,  G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

CPC classification number: G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11862267B2

公开(公告)日：2024-01-02

申请号：US16286246

申请日：2019-02-26

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/10 ,  G11C29/12 ,  G11C5/04

CPC classification number: G11C29/10 ,  G11C29/12 ,  G11C5/04

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.