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公开(公告)号：US11527508B2
公开(公告)日：2022-12-13
申请号：US17174177
申请日：2021-02-11
IPC分类号： H01L25/065 , H01L25/00
摘要： Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.
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公开(公告)号：US20210391305A1
公开(公告)日：2021-12-16
申请号：US17349657
申请日：2021-06-16
IPC分类号： H01L25/065 , H01L25/18
摘要： Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.
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公开(公告)号：US20210318956A1
公开(公告)日：2021-10-14
申请号：US17356906
申请日：2021-06-24
发明人： Brent Keeth , Owen Fay , Chan H. Yoo , Roy E. Greeff , Matthew B. Leslie
IPC分类号： G06F12/06 , G11C29/12 , G11C11/4093 , H01L25/18 , H01L25/065 , G06F12/02
摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
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公开(公告)号：US20210280557A1
公开(公告)日：2021-09-09
申请号：US17174177
申请日：2021-02-11
IPC分类号： H01L25/065 , H01L25/00
摘要： Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.
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公开(公告)号：US20210240357A1
公开(公告)日：2021-08-05
申请号：US17239460
申请日：2021-04-23
发明人： Timothy Hollis , Roy E. Greeff
摘要： Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.
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公开(公告)号：US20190013809A1
公开(公告)日：2019-01-10
申请号：US16130900
申请日：2018-09-13
发明人： Roy E. Greeff
IPC分类号： H03K19/00 , H04L25/02 , H03K19/0185 , H03K5/1534 , H03K19/003
CPC分类号： H03K19/0005 , H03K5/1534 , H03K19/00323 , H03K19/018521 , H04L25/0286
摘要： Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.
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公开(公告)号：US11626145B2
公开(公告)日：2023-04-11
申请号：US17360922
申请日：2021-06-28
摘要： Embodiments of the disclosure include signal processing methods to reduce crosstalk between signal lines of a channel bus using feed forward equalizers (FFEs) configured smear pulse response energy transmitted on signal lines of the channel to reduce pulse edge rates. The coefficients for the FFE may be based on crosstalk interference characteristics. Smearing or spreading pulse response energy across a longer time period using a FFE increases inter-symbol interference (ISI). To counter increased inter-symbol interference caused by smearing pulse response energy, receivers configured to recover symbol data transmitted on the channel bus may each include respective decision-feedback equalizers (DFEs) that are configured to filter ISI from transmitted symbols based on previous symbol decisions of the channel. The combination of the FFE configured to smear pulse responses and the DFE to filter ISI may improve data eye quality for recovery of transmitted data on a channel bus when crosstalk dominates noise.
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公开(公告)号：US20220342814A1
公开(公告)日：2022-10-27
申请号：US17861627
申请日：2022-07-11
发明人： Brent Keeth , Owen Fay , Chan H. Yoo , Roy E. Greeff , Matthew B. Leslie
IPC分类号： G06F12/06 , G11C29/12 , G11C11/4093 , H01L25/18 , H01L25/065 , G06F12/02
摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
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公开(公告)号：US11386004B2
公开(公告)日：2022-07-12
申请号：US16797618
申请日：2020-02-21
发明人： Brent Keeth , Owen Fay , Chan H. Yoo , Roy E. Greeff , Matthew B. Leslie
IPC分类号： G11C16/04 , G06F12/06 , G11C29/12 , G11C11/4093 , H01L25/18 , H01L25/065 , G06F12/02
摘要： Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
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公开(公告)号：US20220004317A1
公开(公告)日：2022-01-06
申请号：US17360943
申请日：2021-06-28
摘要： A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.
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